Method of making the film transistor with all-around gate electrode

• US 5,705,405 A
• Filed: 09/30/1994
• Issued: 01/06/1998
• Est. Priority Date: 09/30/1994
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Cunningham, James A.
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/315,955
• Time in Patent Office: 1,194 Days
• Field of Search: 437/21, 437/40 TFT, 437/40 RG, 437/41 TFT, 437/927, 437/203
• US Class Current: 438/157
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes an insulating support. A strip of semiconductor material has two ends in contact with the insulating support and a midsection extending between the ends. A dielectric layer encircles the midsection, and a conductive layer encircles the dielectric layer. The conductive layer has a substantially constant width such that a gate electrode formed within the conductive layer is fully self-aligned with drain and source regions formed within the ends.

Claims

1. A method of forming a semiconductor device comprising:

forming a strip of semiconductor material on an insulating support;

forming a layer of material on said strip of semiconductor material and on said insulating support;

forming in said layer and in said insulating support an opening around a midsection of said strip;

forming an insulator around said midsection; and

filling said opening with a conductive material to form an electrode around said insulator.

3. The method of claim 1, further comprising doping said midsection to form a channel region and doping ends of said strip adjacent said midsection to form source and drain regions.

4. The method of claim 3, further comprising lightly doping portions of said source and drain regions adjacent said channel region to form lightly doped source and drain regions.

11. The method of claim 1 wherein a source region and a drain region are self aligned to both a portion of said electrode above said midsection and a portion of said electrode beneath said midsection.

2. A method for forming a semiconductor device, comprising:

forming a strip of semiconductor material on an insulating support;

forming a cavity in said insulating support beneath a midsection of said strip by anisotropically etching openings along opposing sides of said midsection and isotropically etching said openings such that said openings merge to form said cavity;

forming an insulator around said midsection; and

forming a self-aligned electrode around said insulator.

5. A method for forming a transistor, comprising:

forming a strip of semiconductor material on an insulating support;

forming a cavity in said insulating support beneath a midsection of said strip such that ends of said strip of semiconductor material adjacent said midsection are in contact with said insulating support;

forming a channel of the transistor within said midsection;

forming a gate insulator around said channel;

forming a gate electrode around said gate insulator, said gate electrode having a first portion outside of said cavity and a second portion inside said cavity; and

forming drain and source regions of the transistor within the respective ones of said ends such that said drain and source regions are self aligned to both of said first and second portions of said gate electrode.

6. The method of claim 5 wherein said step of forming a strip comprises:

forming a layer of polysilicon on said insulating support; and

etching said layer to form said strip.

9. The method of claim 5 wherein said step of forming a gate electrode comprises filling said cavity with an electrically conductive material.

10. The method of claim 5, further comprising lightly doping portions of said drain and source regions adjacent said channel.

7. A method for forming a transistor, comprising:

forming a layer of amorphous silicon on an insulating support;

etching said layer to form a strip having first and second ends;

forming a first dielectric layer over said insulating support and said strip;

forming a second dielectric layer over said first dielectric layer;

flowing said first and second dielectric layers to form a planar surface and to convert said amorphous silicon into polysilicon;

forming a cavity in said insulating support beneath a midsection of said strip such that said ends of said strip contact said insulating support;

forming a channel of the transistor within said midsection;

forming a gate insulator around said channel;

forming a gate electrode around said gate insulator, said gate electrode having a first portion outside of said cavity and a second portion inside of said cavity; and

forming drain and source regions of the transistor within respective ones of said ends such that said drain and source regions are self-aligned to both of said first and second portions of said gate electrode.

8. A method for forming a transistor, comprising:

forming a strip of semiconductor material on an insulating support, said strip having first and second end regions;

forming on said strip and said insulating support a layer having a substantially planar surface;

forming on said layer a mask that exposes a midsection of said strip;

anisotropically etching said layer and said insulating support to form openings that are adjacent to sides of said midsection;

isotropically etching said insulating support such that said openings merge beneath said midsection to form a cavity and such that said end regions of said strip contact said insulating support;

forming a channel of the transistor within said midsection;

forming a gate insulator around said channel;

forming a gate electrode around said gate insulator, said gate electrode having a first portion outside of said cavity and a second portion inside of said cavity; and

forming drain and source regions of the transistor within respective ones of said end regions such that said drain and source regions are self-aligned to both of said first and second portions of said gate electrode.

12. A method of forming a semiconductor device comprising:

forming a strip of semiconductor material on a dielectric support;

forming a cavity in said dielectric support beneath a midsection of said strip;

forming an insulator around said midsection; and

forming an electrode around said insulator such that a first portion of said electrode that is disposed above said midsection is self aligned to a second portion of said electrode that is disposed within said cavity and below said midsection.

13. The method of claim 12, further comprising forming in said strip source region that is adjacent to a first end of said midsection and a drain region that is adjacent to a second end of said midsection, the drain and source regions being self aligned to both of said first and second portions of said electrode.

14. The method of claim 13, further comprising forming adjacent to the respective first and second ends of said midsection lightly doped portions of said source and drain regions.