Method for forming trench transistor structure

• US 5,705,409 A
• Filed: 09/28/1995
• Issued: 01/06/1998
• Est. Priority Date: 09/28/1995
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Witek, Keith E.
• Primary Examiner(s): Tsai, Jey
• Assistant Examiner(s): Pham, Long
• Application Number:
  US08/535,397
• Time in Patent Office: 831 Days
• Field of Search: 437/34, 437/52, 437/56, 437/57, 437/58, 437/90, 437/915
• US Class Current: 438/212
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78657 SOS transistors
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Claims

1. A method for forming a semiconductor device, the method comprising:

providing a substrate;

forming a trench region within the substrate, the trench region having an annular-shaped sidewall;

forming a P-doped channel region adjacent a first portion of the annular-shaped sidewall;

forming an N-doped channel region adjacent a second portion of the annular-shaped sidewall, wherein the first portion and the second portion are physically different regions; and

forming a gate electrode adjacent the annular-shaped sidewall to control current flow in both the N-doped channel region and the P-doped channel region.

2. The method of claim 1 wherein one of either the P-doped channel region or the N-doped channel region is doped via a tilt ion implant process.

3. The method of claim 1 wherein one of either the P-doped channel region or the N-doped channel region is formed via a deep well ion implant and thermal cycle process.

4. The method of claim 1 wherein one of either the P-doped channel region or the N-doped channel region is formed via an insitu doped epitaxially grown region.

5. The method of claim 1 wherein the P-doped channel region is formed adjacent an N-doped current electrode and the N-doped channel region is formed adjacent a P-doped current electrode.

6. The method of claim 5 wherein the P-doped current electrode and the N-doped current electrode share a common interface.

7. The method of claim 6 wherein the N-doped current electrode is laterally adjacent the P-doped current electrode.

8. The method of claim 5 wherein the P-doped current electrode and the N-doped current electrode share a common interface wherein this common interface is silicided to reduce a voltage drop between the P-doped current electrode and the N-doped current electrode.

9. The method of claim 5 wherein either:

(1) the N-doped current electrode is underlying the P-doped current electrode;

or (2) the N-doped current electrode is overlying the P-doped current electrode.

10. The method of claim 1 wherein the gate electrode is formed by depositing a conformal conductive layer and etching the conformal conductive layer to form a conductive spacer around the annular-shaped sidewall to function as the gate electrode.

11. The method of claim 10 wherein a masking layer is used to mask a portion of the conformal conductive layer outside the trench region to create a conductive tab region from the conformal conductive layer wherein the conductive tab region is coupled to the conductive spacer.

12. The method of claim 1 wherein a gate dielectric layer separates the gate electrode from both the P-doped channel region and the N-doped channel region.

13. The method of claim 1 wherein a conductive surface area is coupled to the gate electrode wherein the conductive surface area is outside of the trench region wherein the conductive surface area is used to form an electrical contact region so that the gate electrode can be electrically biased.

14. The method of claim 1 wherein a plug region is formed within the trench region and within an inner circumference of the gate electrode to at least partially fill the trench region.

15. The method of claim 1 wherein a plug region is formed within the trench region and within an inner circumference of the gate electrode to fill the trench region so that an ion implant process used to form a current electrode at a top surface of the substrate does not significantly implant a bottom portion of the trench.

16. The method of claim 1 wherein an N-doped current electrode is formed adjacent the first portion of the annular-shaped sidewall and overlying the P-doped channel region.

17. The method of claim 1 wherein a P-doped current electrode is formed adjacent the second portion of the annular-shaped sidewall and overlying the N-doped channel region.

18. A method for forming a semiconductor device, the method comprising:

providing a substrate;

forming a first doped buried region of a first conductivity type within the substrate;

forming a second doped buried region adjacent the first doped buried region, the second doped buried region being of a second conductivity type;

forming a semiconductor region over the second doped buried region;

doping the semiconductor region such that;

(1) a first portion of the semiconductor region is doped having the first conductivity type wherein the first portion of the semiconductor region overlies a portion of the second doped buried region; and

(2) a second portion of the semiconductor region is doped having the second conductivity type wherein the second portion of the semiconductor region overlies a portion of the first doped buried region, the first portion of the semiconductor region being in close proximity to the second portion of the semiconductor region to form an interface region therebetween;

forming a trench region having a sidewall and a bottom surface, the trench region being formed through the interface region to expose the first portion of the semiconductor region with a first portion of the sidewall of the trench region, expose the second portion of the semiconductor region with a second portion of the sidewall of the trench region, and expose the first doped buried region with the bottom surface of the trench region;

forming an oxide over the trench sidewall and bottom surface;

depositing a conductive layer of material;

etching the conductive layer of material to form a gate sidewall spacer adjacent the sidewall;

forming a first doped region of the second conductivity type above the first portion of the semiconductor region; and

forming a second doped region of the first conductivity type overlying the first portion of the semiconductor region, wherein the gate sidewall spacer controls current flow through the first portion of the semiconductor region adjacent the sidewall of the trench region and the second portion of the substrate adjacent the sidewall of the trench region.

19. The method of claim 18 wherein the step of forming a second doped buried region adjacent the first doped buried region comprises:

forming the second doped buried region overlying and in contact with the first doped buried region.

20. The method of claim 18 wherein the step of forming a second doped buried region adjacent the first doped buried region comprises:

forming the second doped buried region laterally adjacent and in contact with the first doped buried region.

21. The method of claim 18 wherein the step of forming a second doped buried region adjacent the first doped buried region comprises:

forming a metallic region between the second doped buried region and the first doped buried region to reduce a voltage drop between the first doped region and the second doped region.

22. The method of claim 18 wherein the gate sidewall spacer is annular in shape and the method further comprises the step of:

forming a dielectric plug region within a circumference of the gate sidewall spacer.

23. The method of claim 18 wherein one of either the step of forming the first doped buried region or the step of forming the second doped buried region comprises:

forming one of either the first doped buried region or the second doped buried region by implanting dopant atoms into a substrate portion and epitaxially growing substrate material over the dopant atoms.

24. A method for forming a semiconductor device, the method comprising the steps of:

providing a substrate having a surface;

forming a doping barrier layer overlying the substrate, the doping barrier layer having an opening which exposes a portion of the substrate to define a first exposed substrate portion, a second exposed substrate portion, and a third exposed substrate portion wherein the first and third exposed substrate portions of the substrate are separated by the second exposed substrate portion;

forming a trench region within the second exposed substrate portion, the trench region being used to form at least one vertical transistor device;

doping the first exposed substrate portion with N-type dopant atoms; and

doping the second exposed substrate portion with P-type dopant atoms.

25. The method of claim 24 wherein the step of forming the trench region comprises:

forming both a P-type electrode and an N-type electrode at a bottom portion of the trench region.

26. The method of claim 25 wherein the step of forming the trench region comprises:

defining a first channel region between the P-type electrode and the second exposed substrate portion which is doped with P-type dopant atoms, and defining a second channel region between the N-type electrode and the first exposed portion which is doped with N-type dopant atoms.

27. The method of claim 26 wherein the step of forming the trench region comprises:

forming a gate electrode annular spacer within the trench region to control current flow through both the first channel region and the second channel region.

28. A method for forming a semiconductor device, the method comprising the steps of:

providing a substrate having a top surface;

forming a trench region within the substrate having a sidewall and a bottom portion, the sidewall having a first half and a second half;

forming a first conductive region at the bottom portion of the trench region and within the substrate;

forming a second conductive region adjacent the first half of the sidewall and adjacent a top surface of the substrate;

forming a third conductive region adjacent the second half of the sidewall and adjacent a top surface of the substrate, the second and third conductive regions being physically separated from one another by the trench region;

forming a first conductive sidewall spacer within the trench having a first height laterally adjacent first half of the sidewall and a second height laterally adjacent the second half of the sidewall wherein the first height is greater than the second height; and

forming a second conductive sidewall spacer within the trench region and adjacent the first conductive sidewall spacer.

29. The method of claim 28 wherein the step of forming the first conductive sidewall spacer comprises:

forming the first conductive sidewall spacer such that the second height is zero wherein the spacer adjacent the second half of the sidewall is completely removed.

30. The method of claim 28 wherein the step of forming the first conductive sidewall spacer comprises:

defining a channel region between the first and second conductive regions, the channel region being gated by the first conductive sidewall spacer.

31. The method of claim 28 wherein the step of forming the first conductive sidewall spacer comprises:

defining a first channel region between the first and third conductive regions the first channel region being gated by the second conductive sidewall spacer.

32. The method of claim 31 wherein the step of forming the first conductive sidewall spacer comprises:

defining a second channel region between the first and second conductive regions, the second channel region being gated by the first conductive sidewall spacer.

33. The method of claim 28 further comprising the step of:

forming a central transistor through a middle portion of the second conductive sidewall spacer wherein a channel region of the central transistor is gated by the second conductive sidewall spacer.

34. The method of claim 33 wherein the step of forming the central transistor comprises:

forming the central transistor as a P-channel transistor coupled to the first conductive region and wherein the first, second, and third conductive regions form current electrodes for two serially coupled N-channel transistors.

35. The method of claim 33 wherein the step of forming the central transistor comprises:

forming the central transistor wherein the central transistor is coupled to the first conductive region.

36. The method of claim 28 wherein the step of forming the first conductive sidewall spacer comprises:

forming a first contact tab region coupled to the first conductive sidewall spacer to allow for electrical contact to the first conductive sidewall spacer.

37. The method of claim 28 wherein the step of forming the second conductive sidewall spacer comprises:

forming a first contact tab region coupled to the second conductive sidewall spacer to allow for electrical contact to the second conductive sidewall spacer.

38. A method for forming a semiconductor device, the method comprising the steps of:

providing a substrate having a top surface, the substrate having a first area, a second area, and a third area wherein the first area is laterally adjacent the

second area and the second area is laterally adjacent the third area;

forming a first N-channel transistor within the first area of the substrate wherein the first N-channel transistor has a channel region wherein current flows substantially vertically through the channel region;

forming a second N-channel transistor within the third area of the substrate wherein the second N-channel transistor has a channel region wherein current flows substantially vertically through the channel region;

forming a P-channel transistor within the second area of the substrate wherein the P-channel transistor has a channel region wherein current flows substantially vertically through the channel region; and

wherein the P-channel transistor, the first N-channel transistor, and the second N-channel transistor all connect to a common node formed within the substrate.

39. A method for forming a semiconductor device, the method comprising the steps of:

forming a first N-type region of substrate material;

forming a first P-type region overlying the first N-type region wherein the first P-type region abuts the first N-type region and is made of the substrate material;

forming a second N-type region overlying the first P-type region wherein the second N-type region abuts the first P-type region and is made of the substrate material;

forming a second P-type region overlying the second N-type region wherein the second P-type region abuts the first N-type region and is made of the substrate material;

forming a dielectric layer overlying the second P-type region;

etching an opening through the dielectric layer, the first and second P-type regions, and the second N-type region to expose a portion of the first N-type region, the opening having a sidewall;

forming a sidewall dielectric layer laterally adjacent the sidewall of the opening; and

forming a conductive layer within the opening which connects to the first N-type region.

40. The method of claim 39 further comprising the step of:

implanting additional N type dopant into the first N-type region of substrate material after etching the opening.

41. The method of claim 39 wherein the first and second N-type regions are coupled as current electrodes for a vertical transistor.

42. The method of claim 39 wherein the first and second P-type regions are current electrodes for a vertical transistor.

43. A method for forming a semiconductor device, the method comprising the steps of:

forming a first P-type region of substrate material;

forming a first N-type region above the first P-type region wherein the first N-type region abuts the first P-type region and is made of the substrate material;

forming a second P-type region above the first N-type region wherein the second P-type region abuts the first N-type region and is made of the substrate material;

forming a second N-type region above the second P-type region wherein the second N-type region abuts the first P-type region and is made of the substrate material;

forming a dielectric layer above the second N-type region;

etching an opening through the dielectric layer, the first and second N-type regions, and the second P-type region to expose a portion of the first P-type region, the opening having a sidewall;

forming a sidewall dielectric layer laterally adjacent the sidewall of the opening; and

forming a conductive layer within the opening which connects to the first P-type region.

44. A method for forming a semiconductor device, the method comprising the steps of:

forming a first doped region within a substrate;

forming a second doped region above the first doped region wherein the second doped region abuts the first doped region and is made of the substrate material, the second doped region being of a first conductivity type;

forming a third doped region above the second doped region wherein the third doped region abuts the second doped region and is made of substrate material, the second doped region being of a second conductivity type different from the first conductivity type;

forming a dielectric layer above the third doped region;

etching an opening through the dielectric layer, the second doped region and the third doped region to expose a portion of the first doped region, the opening having a sidewall;

forming a sidewall dielectric layer laterally adjacent the sidewall of the opening; and

forming a conductive layer within the opening which connects to the first doped region.

45. The method of claim 44 wherein the step of forming the first doped region comprises:

forming the first doped region as a first P-doped portion and a second N-doped portion that are adjacent and in contact with one another.

46. The method of claim 44 wherein the step of forming the first doped region comprises:

forming the first doped region a first P-doped portion and a second N-doped portion that are adjacent and in contact with one another; and

forming a metallic interface region between the first P-doped portion and the second N-doped portion to reduce a voltage drop between the first P-doped portion and the second N-doped portion.

47. A method for forming a transistor structure comprising the steps of:

providing a substrate;

forming a trench region within the substrate, the trench region having a top portion, a bottom portion, a sidewall, a first half and a second half;

forming a first doped current electrode at a bottom portion of the trench region;

forming a second doped current electrode at a top portion of the trench region, a channel region being defined between the first and second doped current electrodes and adjacent the first half of the trench region;

forming an annular conductive sidewall conductor within the trench region wherein the second annular conductive sidewall conductor controls a current flow through the channel region; and

reducing a height of the annular conductive sidewall conductor so that a height of the annular conductive sidewall conductor adjacent the first half of the trench region is greater than a height of the annular conductive sidewall conductor adjacent the second half of the trench region.

48. The method of claim 47 wherein the height of the annular conductive sidewall conductor adjacent the second half of the trench region is reduced to zero via etching.