Process for forming an electrically programmable read-only memory cell

• US 5,705,415 A
• Filed: 10/04/1994
• Issued: 01/06/1998
• Est. Priority Date: 10/04/1994
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Orlowski, Marius K., Chang, Ko-Min
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/324,423
• Time in Patent Office: 1,190 Days
• Field of Search: 437/43, 437/203, 437/52
• US Class Current: 438/259
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device is formed having a floating gate memory cell (11) that has its channel region (33) oriented vertically with a portion of the channel region (33) that is not capacitively coupled to a floating gate (32). The memory cell (11) is less likely to be over-erased and may be programmed by source-side injection. The cell (11) may not need to be repaired after erasing. Less power may be consumed during programming compared to hot electron injection and Fowler-Nordheim tunneling.

Claims

1. A process for forming a semiconductor device including an electrically programmable read-only memory cell comprising the steps of:

forming a vertical edge adjacent to a primary surface of a semiconductor substrate;

forming a first doped region and a second doped region, wherein;

the first doped region lies adjacent to the vertical edge and spaced apart from the primary surface;

the second doped region lies adjacent to the vertical edge and the primary surface, wherein a bottom of the second doped region at the vertical edge lies at a first elevation; and

a channel region adjacent to the vertical edge that lies between the first and second doped regions, wherein the channel region includes a first portion adjacent to the first doped region and a second portion adjacent to the second doped region;

forming a floating gate adjacent to the first portion of the channel region, wherein;

the floating gate has a highest point adjacent to the vertical edge; and

the highest point lies at a second elevation that is lower than and spaced apart from the first elevation; and

the step of forming the floating gate is performed after the step of forming the vertical edge;

forming a control gate adjacent to the first doped region; and

forming a select gate adjacent to the control gate and the second portion of the channel region.

2. The process of claim 1, wherein the first doped region and the second doped region are formed during separate steps.

3. The process of claim 1, wherein:

another electrically programmable read-only memory cell is formed during the process and includes a different vertical edge and a different floating gate;

the step of forming the vertical edge is performed such that both the first mentioned vertical edge and the different vertical edge are part of a trench; and

the step of forming the floating gate is performed such that the floating gates lie within the trench.

13. The process of claim 1, wherein the steps of forming the vertical edge and forming the select gate are performed such that the vertical edge has a length that extends in a first direction, the select gate has a length that extends in a second direction that is perpendicular to the first direction.

14. The process of claim 1, wherein the step of forming the vertical edge is performed by etching a trench into the substrate to a depth no greater than one micron.

15. The process of claim 14, wherein the steps of forming the floating gate and the control gate are performed such that the floating gate and the control gate lie completely within the trench.

16. The process of claim 15, wherein the step of forming the select gate is performed such that the select gate lies completely within the trench.

17. The process of claim 1, wherein:

the step of forming the vertical edge includes a step of etching a trench into the semiconductor substrate; and

the step of forming the floating gate includes steps of;

depositing a semiconductor material within the trench; and

etching the semiconductor material to form a spacer that defines the floating gate.

18. The process of claim 1, further comprising a step of forming a field isolation region along the vertical edge and adjacent to the floating gate.

19. The process of claim 1, wherein the step of forming the floating gate is performed such that the floating gate has a height that is in a range of 50-90 percent of a height of the vertical edge.

20. The process of claim 1, wherein the steps of forming the floating gate and the first and second doped regions are performed such that a difference between the first and second elevations is in a range of 0.05-0.45 microns.

4. A process for forming a semiconductor device including an electrically programmable read-only memory cell comprising the steps of:

forming a vertical edge adjacent to a primary surface of a semiconductor substrate;

forming a first doped region, a second doped region and a third doped region, wherein;

the first doped region lies adjacent to the vertical edge and spaced apart from the primary surface;

the second doped region lies adjacent to the vertical edge and the primary surface, wherein a bottom of the second doped region at the vertical edge lies at a first elevation;

a channel region adjacent to the vertical edge and lies between the first and second doped regions, wherein the channel region includes a first portion adjacent to the first doped region and a second portion adjacent to the second doped region; and

the third doped region lies adjacent to the primary surface and is spaced apart from the second doped region;

forming a floating gate adjacent to the first portion of the channel region, wherein;

the floating gate has a highest point adjacent to the vertical edge; and

the highest point lies at a second elevation that is lower than and spaced apart from the first elevation; and

the step of forming the floating gate is performed after the step of forming the vertical edge;

forming a control gate adjacent to the floating gate; and

forming a select gate adjacent to the primary surface, the second doped region, and third doped region.

5. The process of claim 4, further comprising a step of forming a field isolation region, wherein said step is performed after the step of forming the floating gate.

6. The process of claim 4, wherein:

another electrically programmable read-only memory cell is formed during the process and includes a different vertical edge and a different floating gate;

the step of forming both vertical edges is performed such that the first mentioned vertical edge and the different vertical edge define sides of a trench; and

the step of forming the floating gate is performed such that the first mentioned floating gate and the different floating gate lie within the trench.

7. The process of claim 4, wherein the step of forming the vertical edge is performed by etching a trench into the substrate to a depth no greater than one micron.

8. The process of claim 4, wherein:

the step of forming the vertical edge includes a step of etching a trench into the semiconductor substrate; and

the step of forming the floating gate includes steps of;

depositing a semiconductor material within the trench; and

etching the semiconductor material to form a spacer that defines the floating gate.

9. The process of claim 4, further comprising a step of forming a field isolation region along the vertical edge and adjacent to the floating gate.

10. The process of claim 4, wherein the step of forming the floating gate is performed such that the floating gate has a height that is in a range of 50-90 percent of a height of the vertical edge.

11. The process of claim 4, wherein the steps of forming the floating gate and forming the first and second doped regions are performed such that

a difference between the first and second elevations is in a range of 0.05-0.45 microns.

12. The process of claim 4, wherein the steps of forming the vertical edge and forming the select gate are performed such that the vertical edge has a length that extends in a first direction and the select gate has a length that also extends in the first direction.

21. A process for forming a semiconductor device including an electrically programmable read-only memory cell comprising the steps of:

forming a vertical edge adjacent to a primary surface of a semiconductor substrate;

forming a first doped region, a second doped region and a third doped region, wherein;

the first doped region lies adjacent to the vertical edge and spaced apart from the primary surface;

the second doped region lies adjacent to the vertical edge and the primary surface;

a channel region adjacent to the vertical edge and lies between the first and second doped regions; and

the third doped region lies adjacent to the primary surface and is spaced apart from the second doped region;

forming a floating gate adjacent to a first portion of the channel region, wherein the first portion is less than all of the channel region;

forming a field isolation region after the step of forming the floating gate;

forming a control gate adjacent to the floating gate but not the channel region; and

forming a select gate adjacent to the primary surface, the second doped region, and third doped region.

22. A process for forming a semiconductor device including an electrically programmable read-only memory cell comprising the steps of:

forming a vertical edge adjacent to a primary surface of a semiconductor substrate;

forming a first doped region, a second doped region and a third doped region, wherein;

the first doped region lies adjacent to the vertical edge and spaced apart from the primary surface;

the second doped region lies adjacent to the vertical edge and the primary surface;

a channel region adjacent to the vertical edge and lies between the first and second doped regions; and

the third doped region lies adjacent to the primary surface and is spaced apart from the second doped region;

forming a floating gate adjacent to a first portion of the channel region, wherein the first portion is less than all of the channel region;

forming a field isolation region along the vertical edge and adjacent to the floating gate;

forming a control gate adjacent to the floating gate but not the channel region; and

forming a select gate adjacent to the primary surface, the second doped region, and third doped region.

23. A process for forming a semiconductor device including an electrically programmable read-only memory cell comprising the steps of:

forming a vertical edge adjacent to a primary surface of a semiconductor substrate;

forming a first doped region and a second doped region, wherein;

the first doped region lies adjacent to the vertical edge and spaced apart from the primary surface;

the second doped region lies adjacent to the vertical edge and the primary surface; and

a channel region adjacent to the vertical edge and lies between the first and second doped regions;

forming a floating gate adjacent to a first portion of the channel region;

forming a field isolation region along the vertical edge and adjacent to the floating gate;

forming a control gate adjacent to the first doped region; and

forming a select gate adjacent to;

the control gate; and

a second portion of the channel region that is different from the first portion of the channel region.