Clock generator

• US 5,705,947 A
• Filed: 12/29/1995
• Issued: 01/06/1998
• Est. Priority Date: 06/06/1994
• Status: Expired due to Term

• Current Assignee: Deog-Kyoon Jeog, Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Deog-Kyoon Jeog, Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Jeong, Deog-Kyoon
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): KIM, JUNG H
• Application Number:
  US08/580,569
• Time in Patent Office: 739 Days
• Field of Search: 327/157, 327/158, 327/270, 327/149, 327/276, 331/17, 331/25, 331/57
• US Class Current: 327/270
• CPC Class Codes: H03K 19/018592 with a bidirectional operation
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 5/1423 for simultaneous baseband signals
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Claims

1. A circuit for generating a series of high speed clock signals comprising:

a reference clock signal; and

a phase frequency detector coupled to receive the reference clock signal and an output of one of a plurality of delay cells and in response thereto, supply a first control voltage indicative of a phase difference between the reference clock signal and the output of one of the plurality of delay cells, the first control voltage varying from a first potential to a second potential, and a second control voltage, indicative of a phase difference between the reference clock signal and the output of one of the plurality of delay cells, the second control voltage varying from the second potential to the first potential,

wherein the plurality of delay cells are serially connected stages, each cell supplying a clock signal in response to changes in the first and second phase frequency detector control voltages, each cell connected to receive the clock signal from a preceding cell and supply it to a following cell after delaying it, and a last cell feeding back to a first cell in the plurality, whereby the clock signals from the plurality of delay cells forms a series of multiple subfrequency clock signals evenly spaced from the reference clock signal, wherein a delay cell comprises;

a first transistor, coupled between the first potential and a first node having a control electrode coupled to the first node;

a second transistor, coupled between the first node and an output node, having a control electrode coupled to a first bias voltage;

a third transistor, coupled between the output node and a second node, having a control electrode coupled to an output of one of the plurality of delay cells; and

a fourth transistor, coupled between the second node and the second potential, having a control electrode coupled to a second bias voltage.

2. The circuit of claim 1 further comprising:

a loop filter wherein the first control voltage and the second control voltage are coupled through the loop filter to the plurality of serially connected stages of delay cells.

3. The circuit of claim 1 wherein the first control voltage and the second control voltage are fed back through the plurality of serially connected stages of delay cells to the phase frequency detector.

4. The circuit of claim 1 further comprising:

a charge pump and loop filter coupled to the first control voltage and the second control voltage, supplying a third control voltage to the plurality of serially connected stages of delay cells wherein the third control voltage varies the speed of the delay cells.

5. The circuit of claim 1 further comprising:

two parallel buffers wherein the two parallel buffers generate from the series of multiple subfrequency clock signals a first group of equally spaced clocks and a second group of equally spaced clocks.

6. The circuit of claim 4 wherein the charge pump and loop filters comprises:

a first transistor, coupled between an output node and a first current source, and having a control electrode coupled to the first control voltage; and

a second transistor, coupled between the output node and a second current source, and having a control electrode coupled to the second control voltage, whereby the third voltage is generated at the output node and the first current source and second current source maintain a constant relationship.

8. The circuit of claim 1 further comprising:

a replica bias circuit, coupled to the plurality of serially connected stages of delay cells, wherein the replica bias circuit minimizes switching effects of the delay cells on the series of multiple subfrequency clock signals.

14. The circuit of claim 1 wherein a frequency of the output from one of the plurality of delay cells is at least divided by two before being received by the phase frequency detector.

7. A circuit for generating a series of high speed clock signals comprising:

a reference clock signal; and

a phase frequency detector coupled to receive the reference clock signal and an output of one of a plurality of delay cells and in response thereto, supply a first control voltage, indicative of a phase difference between the reference clock signal and the output of one of the plurality of delay cells, the first control voltage varying from a first potential to a second potential, and a second control voltage, indicative of a phase difference between the reference clock signal and the output of one of the plurality of delay cells, the second control voltage varying from the second potential to the first potential,

wherein the plurality of delay cells are serially connected stages, each cell supplying a clock signal in response to changes in the first and second phase frequency detector control voltages, each cell connected to receive the clock signal from a preceding cell and supply it to a following cell after delaying it, a last cell feeding back to a first cell in the plurality, whereby the clock signals from the plurality of delay cells forms a series of multiple subfrequency clock signals evenly spaced from the reference clock signal, wherein each delay cell comprises;

a first transistor, coupled between the first potential and a first node, having a control electrode coupled to the first node;

a second transistor, coupled between the first node and a first output node, having a control electrode coupled to a first bias voltage;

a third transistor, coupled between the first node and a second output node, having a control electrode coupled to the first bias voltage, wherein the second output node provides an inverse of a signal at the first output node;

a fourth transistor, coupled between the first output node and a second node, having a control electrode coupled to an output of one of the plurality of delay cells;

a fifth transistor, coupled between the second output node and the second node, having a control electrode coupled to an inverse of the output of one of the plurality of delay cells; and

a sixth transistor, coupled between the second node and the second potential, having a control electrode coupled to a second bias voltage.

9. A circuit for generating a series of high speed clock signals comprising:

a reference clock signal;

a phase frequency detector, generating a control signal indicating a phase difference between a first edge of the reference clock signal and a selected clock signal of the series of high speed clock signals;

a first delay cell, generating a first output signal and a second output signal, wherein the first delay cell is coupled to an output signal from a second delay cell and an inverse of the second delay cell output signal, wherein the first delay cell decreases its switching time as the control signal increases, and the first delay cell increases its switching time as the control signal decreases, and the first delay cell comprises;

a first transistor, coupled between the first potential and a first node having a control electrode coupled to the first node;

a second transistor, coupled between the first node and an output node, having a control electrode coupled to a first bias voltage;

a third transistor, coupled between the output node and a second node, having a control electrode coupled to an output of one of the plurality of delay cells; and

a fourth transistor, coupled between the second node and the second potential, having a control electrode coupled to a second bias voltage.

10. The circuit of claim 9 further comprising:

a replica bias, generating a replica bias output, coupled to the at least one delay cell, wherein the replica bias stabilizes the voltage on the delay cell by compensating for an impact of switching transients on the delay cell.

11. The circuit of claim 9 further comprising:

a plurality of delay cells, each of the delay cells coupled to the first output signal and the second output signal of a preceding delay cell, wherein the plurality of delay cells is used to generate a plurality of equally spaced clock signals, each of a slightly different phase than the preceding clock signal.

12. The circuit of claim 10 wherein the delay cell contains a first voltage controlled resistor, and the replica bias contains a second voltage controlled resistor, having a similar structure as the first voltage controlled resistor, whereby the delay cell tracks the replica bias through a relationship between the first voltage controlled resistor and the second voltage controlled resistor.

13. The circuit of claim 9 wherein the first clock signal is fed back to the phase frequency detector through a frequency divider.

15. A circuit for generating a series of high speed clock signals comprising:

a reference clock signal;

a phase frequency detector coupled to receive the reference clock signal and an output of one of a plurality of serially connected stages of delay cells and in response thereto supply a first control voltage indicative of transitions of the reference clock signal and the output of one of the plurality of delay cells, the first control voltage varying from a first potential to a second potential, and a second control voltage, indicative of transitions of the reference clock signal and the output of one of the plurality of delay cells, the second control voltage varying from the second potential to the first potential;

a charge pump, coupled to the first and the second phase frequency detector control voltages, generating a control signal; and

the plurality of serially connected stages of delay cells, each cell coupled to receive the charge pump control signal and in response thereto supplying a clock signal, each cell connected to receive the clock signal from a preceding cell and supply it to a following cell after delaying it, each delay cell decreasing its switching time when the charge pump control signal increases and increasing its switching time when the charge pump control signal decreases, one of the cells in the plurality supplying a clock signal to a different cell in the plurality, and a cell in the plurality supplying a clock signal to the phase frequency detector, wherein each delay cell comprises;

a first transistor, coupled between the first potential and a first node, having a control electrode coupled to the first node;

a second transistor, coupled between the first node and an output node, having a control electrode coupled to a first bias voltage;

a third transistor, coupled between the output node and a second node, having a control electrode coupled to an output of one of the plurality of delay cells; and

a fourth transistor, coupled between the second node and the second potential, having a control electrode coupled to the control voltage;

whereby a series of multiple subfrequency clock signals is generated which are evenly spaced from the reference clock signal.

16. The circuit of claim 15 wherein the charge pump comprises:

a first transistor, coupled between an output node and a first current source, having a control electrode coupled to the first phase frequency detector control voltage; and

a second transistor, coupled between the output node and a second current source, and having a control electrode coupled to the second phase frequency detector control voltage, wherein the charge pump control voltage is generated at the output node.

18. The circuit of claim 15 further comprising:

a replica bias circuit, coupled to the plurality of serially connected stages of delay cells, wherein the replica bias circuit minimizes switching effects of the delay cells on the series of multiple subfrequency clock signals.

20. The circuit of claim 15 wherein a frequency of the output from one of the plurality of delay cells is at least divided by two before being received by the phase frequency detector.

17. A circuit for generating a series of high speed clock signals comprising:

a reference clock signal;

a phase frequency detector coupled to receive the reference clock signal and an output of one of a plurality of serially connected stages of delay cells and in response thereto supply a first control voltage indicative of transitions of the reference clock signal and the output of one of the plurality of delay cells, the first control voltage varying from a first potential to a second potential, and a second control voltage, indicative of transitions of the reference clock signal and the output of one of the plurality of delay cells, the second control voltage varying from the second potential to the first potential; and

a charge pump, coupled to the first and the second phase frequency detector control voltages, generating a control signal,

wherein each cell of the plurality of serially connected stages of delay cells is coupled to receive the charge pump control signal and in response thereto supply a clock signal, each cell connected to receive the clock signal from a preceding cell and supply it to a following cell after delaying it, each delay cell decreasing its switching time when the charge pump control signal increases, and increasing its switching time when the charge pump control signal decreases, one of the cells in the plurality supplying a clock signal to the phase frequency detector, whereby a series of multiple subfrequency clock signals is generated are evenly spaced from the reference clock signal, wherein each delay cell comprises;

a first transistor, coupled between the first potential and a first node, having a control electrode coupled to the first node;

a second transistor, coupled between the first node and an output node, having a control electrode coupled to a first bias voltage;

a third transistor, coupled between the output node and a second node, having a control electrode coupled to an output of one of the plurality of delay cells; and

a fourth transistor, coupled between the second node and the second potential, having a control electrode coupled to the control signal.

19. A circuit for generating a series of high speed clock signals comprising:

a reference clock signal;

a phase frequency detector coupled to receive the reference clock signal and an output of one of a plurality of serially connected stages of delay cells and in response thereto supply a first control voltage indicative of transitions of the reference clock signal and the output of one of the plurality of delay cells from a first potential to a second potential, and a second control voltage indicative of transitions of the reference clock signal and the output of one of the plurality of delay cells from the second potential to the first potential;

a charge pump, coupled to the first and the second phase frequency detector control voltages, generating a control signal,

wherein each cell of the plurality of serially connected stages of delay cells is coupled to receive the charge pump control signal and in response thereto supplying a clock signal, each cell connected to receive the clock signal from a preceding cell and supply it to a following cell after delaying it, each delay cell decreasing its switching time when the charge pump control signal increases and increasing its switching time when the charge pump control signal decreases, one of the cells in the plurality supplying a clock signal to a different cell in the plurality, and a cell in the plurality supplying a clock signal to the phase frequency detector, whereby a series of multiple subfrequency clock signals is generated which multiple subfrequency clock signals are evenly spaced from the reference clock signal;

a replica bias circuit, coupled to the plurality of serially connected stages of delay cells, wherein the replica bias circuit minimizes switching effects of the delay cells on the series of multiple subfrequency clock signals, and comprises;

a first transistor, coupled between the first potential and a first node, having a control electrode coupled to the first node;

a second transistor, coupled between the first node and an output node, having a control electrode coupled to a first bias voltage;

a third transistor, coupled between the output node and a second node, having a control electrode coupled to a second bias voltage; and

a fourth transistor, coupled between the second node and the second potential, having a control electrode coupled to the control signal.

21. A circuit for generating a series of high speed clock signals comprising:

a reference clock signal;

a phase frequency detector coupled to receive the reference clock signal and an output from a first delay cell and in response thereto generating a control signal; and

a second delay cell, coupled to the control signal and an output signal from the first delay cell, wherein the second delay cell comprises;

a first transistor, coupled between a first potential and a first node, having a control electrode coupled to the first node;

a second transistor, coupled between the first node and an output node, having a control electrode coupled to a first bias voltage;

a third transistor, coupled between the output node and a second node, having a control electrode coupled to an output of one of the at least one delay cell; and

a fourth transistor, coupled between the second node and a second potential, having a control electrode coupled to the control signal.