Frequency locked-loop using a microcontroller as a comparator

• US 5,705,955 A
• Filed: 12/21/1995
• Issued: 01/06/1998
• Est. Priority Date: 12/21/1995
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Pearce, Anne M., Odlyzko, Paul, Schulz, Gary, Freeburg, Thomas A., Ley, John
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US08/576,520
• Time in Patent Office: 747 Days
• Field of Search: 331/2, 331/14, 331/17, 331/25, 331/185, 331/23, 332/127, 332/128, 332/100-102, 455/343, 375/275, 375/307
• US Class Current: 331/14
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop

Abstract

A frequency-locked loop (100) employs a controllable oscillator (102) for generating an output signal having a frequency, optional sampler (104), coupled to oscillator (102), for sampling the frequency of the output signal, a divider (106), coupled to optional sampling circuit (104), for dividing the output signal frequency to generate a prescaled signal and a microprocessor (108), coupled between the divider 106 and oscillator (102), for comparing the prescaled signal to a reference signal and generating a control signal for correcting frequency shifts based upon the comparison. The control signal generated by microprocessor (108) is non-continuous. During that time when microprocessor (108) generates no control signals, power is removed from various frequency-locked loop circuitry.

Claims

1. A frequency-locked loop comprising:

a controllable oscillator for generating an output signal having a frequency the controllable oscillator having an input receiving a modulation signal in a transmission mode;

a sampler, coupled to the controllable oscillator, for sampling the frequency of the output signal;

a divider, coupled to the sampler, for dividing the frequency of the output signal to generate a prescaled signal;

a microprocessor, coupled to the divider and the controllable oscillator, for performing a comparison of the prescaled signal to a reference signal and generating a non-continuous signal for correcting the frequency of the controllable oscillator output signal when not in the transmission mode, the microprocessor having instructions stored therein which control sampling by the sampler;

a converter coupled to the microprocessor for converting the non-continuous control signal to an analog signal;

a low pass filter coupled to the converter for filtering undesired components from the analog signal; and

a summer coupled between the low pass filter and the controllable oscillator in order to provide for injection of the modulation signal.

2. The frequency-locked loop of claim 1, wherein the converter is one of a group consisting of a digital-to-analog converter and a pulse width modulator, the low-pass filter and converter together being operable for converting non-continuous control signals to analog signals for delivery to the controllable oscillator.

3. The frequency-locked loop of claim 1 wherein power resources are removed from the divider when the microprocessor is not generating control signals for communication to the controllable oscillator while continuing to provide the reference signal from a reference signal source.

4. The frequency-locked loop of claim 1 wherein power resources are removed from the sampler when the microprocessor is not generating control signals for communication to the controllable oscillator while continuing to provide the reference signal from a reference signal source.

5. A method for conserving power resources in a transmission circuit, comprising the steps of:

generating an output signal having a variable frequency;

performing, when in a non-transmission mode of operation, a comparison in a microprocessor of a prescaled signal, derived from the output signal, to a reference signal having a frequency, where the reference signal is a clock signal for the microprocessor;

generating a non-continuous control signal for frequency adjusting the output signal based upon the comparison;

operating in a transmission mode; and

removing power resources from at least a portion of the transmission circuit when no control signal is being generated while continuing to provide the reference signal.