Switched control signals for digital micro-mirror device with split reset

• US 5,706,123 A
• Filed: 09/27/1996
• Issued: 01/06/1998
• Est. Priority Date: 09/27/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Mezenner, Rabah, Chu, Henry Chung-Hsin, Cleveland, Harlan Paul, Miller, Rodney D., Gale, Richard O.
• Primary Examiner(s): Font, Frank G.
• Assistant Examiner(s): RATLIFF, REGINALD A
• Application Number:
  US08/720,367
• Time in Patent Office: 466 Days
• Field of Search: 359/291, 359/292, 359/293, 359/296, 359/290, 359/212, 359/221, 359/230, 359/294
• US Class Current: 359/291
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means

Abstract

A method of providing control signals for resetting mirror elements (10,20) of a digital micro-mirror device (DMD) having reset groups (FIG. 4), or for resetting moveable elements of other micro-mechanical devices that operate with similar principles. A bias voltage is applied to the mirrors and their landing sites, and an address voltage is applied under the mirrors. (FIG. 3). The address voltage is held at an intermediate level except during a reset period. During this reset period, the address voltage is increased. Also, during reset, the bias applied to mirrors to be reset is pulsed and offset, and the bias applied to mirrors not to be reset is increased. (FIGS. 5 and 6).

Claims

1. A method of resetting movable elements of a micro-mechanical device, each of said movable elements being attracted toward a landing surface by means of an address voltage, and said moveable elements being grouped into reset groups, comprising the steps of:

applying a bias voltage to said movable elements;

switching each said address voltage of each movable element of one of said reset groups to either a low address level or to an intermediate address level;

after said switching step, resetting said one of said reset groups by adding a reset voltage to said bias voltage and then reducing said bias voltage to an offset bias level;

after said switching step and during said resetting step, increasing said intermediate address level to a high address level; and

after said switching step and during said resetting step, increasing said bias voltage to a high bias level, with respect to all other of said reset groups.

2. The method of claim 1, wherein said moveable elements contact said landing surface at a landing site and wherein said bias voltage is also applied to said landing site.

3. The method of claim 1, wherein said bias is positive.

4. The method of claim 1, wherein said bias is negative and wherein said offset bias level is accomplished by reducing the magnitude of said bias voltage and said high bias level is accomplished by increasing the magnitude of said bias voltage.

5. The method of claim 1, wherein said offset bias level is substantially equal to said high address level.

6. The method of claim 1, wherein said each moveable element is reset to an alternative position and wherein said switching step comprises switching complementary address signals.

7. The method of claim 1, wherein said moveable elements are mirror elements of a DMD.

8. The method of claim 7, wherein said mirror elements are hidden hinge mirror elements and wherein said bias voltage is applied to yokes of said mirror elements and wherein said address voltage is applied under said yokes.

9. The method of claim 1, wherein said moveable elements have memory cells that store data representing the state of said address voltage.

10. The method of claim 9, wherein moveable elements of said one of said reset groups share memory cells with moveable elements of other of said reset groups and wherein said switching step is performed for all of said memory cells.

11. A method of resetting mirror elements of a digital micro-mirror device (DMD), each said of mirror elements being attracted toward a landing surface by means of an address voltage, and said mirror elements being grouped into reset groups, comprising the steps of:

applying a bias voltage to said mirror elements;

switching said address voltage of each mirror element of one of said reset groups to either a low address level or to an intermediate address level;

after said switching step, resetting said one of said reset groups by adding a reset voltage to said bias voltage and then reducing said bias voltage to an offset bias level;

after said switching step and during said resetting step, increasing said intermediate address level to a high address level; and

after said switching step and during said resetting step, increasing said bias voltage to a high bias level, with respect to all other of said reset groups.

12. The method of claim 11, wherein said mirror elements contact said landing surface at a landing site and wherein said bias voltage is also applied to said landing site.

13. The method of claim 11, wherein said bias is positive.

14. The method of claim 11, wherein said bias is negative and wherein said offset bias level is accomplished by reducing the magnitude of said bias voltage and said high bias level is accomplished by increasing the magnitude of said bias voltage.

15. The method of claim 11 wherein said offset bias level is substantially equal to said high address level.

16. The method of claim 11, wherein said each mirror element is reset to an alternative position and wherein said switching step comprises switching complementary address signals.

17. The method of claim 11, wherein said mirror elements are hidden hinge mirror elements and wherein said bias voltage is applied to yokes of said mirror elements and wherein said address voltage is applied under said yokes.

18. The method of claim 11, wherein said moveable elements have memory cells that store data representing the state of said address voltage.

19. The method of claim 18, wherein moveable elements of said one of said reset groups share memory cells with moveable elements of other of said reset groups and wherein said switching step is performed for all of said memory cells.