Method for operating a memory array
First Claim
1. A method for operating a memory array that includes reading a selected memory cell comprising the steps of:
- providing the memory array including a selected memory cell and an unselected memory cell, wherein;
each of the selected and unselected memory cells has an isolation transistor and a floating gate transistor a drain terminal, and a source terminal;
each of the isolation and floating gate transistors has a gate terminal; and
the drain terminals of the selected and unselected memory cells are electrically connected to each other;
applying a first voltage potential having a first polarity to the gate terminal of the floating gate transistor of the selected memory cell;
applying a second voltage potential having the first polarity to the drain terminals of the selected and unselected memory cells; and
applying a third voltage potential having the first polarity to the gate terminal of the floating gate transistor of the unselected memory cell.
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Accused Products
Abstract
A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.
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Citations
12 Claims
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1. A method for operating a memory array that includes reading a selected memory cell comprising the steps of:
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providing the memory array including a selected memory cell and an unselected memory cell, wherein; each of the selected and unselected memory cells has an isolation transistor and a floating gate transistor a drain terminal, and a source terminal; each of the isolation and floating gate transistors has a gate terminal; and the drain terminals of the selected and unselected memory cells are electrically connected to each other; applying a first voltage potential having a first polarity to the gate terminal of the floating gate transistor of the selected memory cell; applying a second voltage potential having the first polarity to the drain terminals of the selected and unselected memory cells; and applying a third voltage potential having the first polarity to the gate terminal of the floating gate transistor of the unselected memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification