Method for operating a memory array

• US 5,706,228 A
• Filed: 02/20/1996
• Issued: 01/06/1998
• Est. Priority Date: 02/20/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Cavins, Craig A., Chang, Kuo-Tung, Chang, Ko-Min, Morton, Bruce L., Espinor, George L.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US08/603,939
• Time in Patent Office: 686 Days
• Field of Search: 365/185.18, 365/185.17, 365/185.24, 365/185.02
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.

Claims

1. A method for operating a memory array that includes reading a selected memory cell comprising the steps of:

providing the memory array including a selected memory cell and an unselected memory cell, wherein;

each of the selected and unselected memory cells has an isolation transistor and a floating gate transistor a drain terminal, and a source terminal;

each of the isolation and floating gate transistors has a gate terminal; and

the drain terminals of the selected and unselected memory cells are electrically connected to each other;

applying a first voltage potential having a first polarity to the gate terminal of the floating gate transistor of the selected memory cell;

applying a second voltage potential having the first polarity to the drain terminals of the selected and unselected memory cells; and

applying a third voltage potential having the first polarity to the gate terminal of the floating gate transistor of the unselected memory cell.

2. The method for operating the memory array of claim 1, further comprising a step of selectively programming the selected memory cell including the steps of:

applying a fourth voltage potential having the first polarity to the drain terminals of the selected and unselected memory cells; and

applying a fifth voltage potential having a second polarity to the gate terminal of the floating gate transistor of the selected memory cell, wherein the second polarity is opposite the first polarity; and

applying a sixth voltage potential having the first polarity to the gate terminal of the floating gate transistor of the unselected memory cell.

3. The method of claim 2, further comprising a step of applying about -5 volts to 5 volts to the source terminal and the gate terminal of the isolation transistor of the selected memory cell.

4. The method of claim 2, wherein:

the step of applying the fourth voltage potential comprises a step of applying about 0.1 volts to 10 volts;

the step of applying the fifth voltage potential comprises a step of applying about -5 volts to -15 volts;

the step of applying the sixth voltage potential comprises a step of applying about 0.1 volts to 10 volts; and

the method further comprises a step applying about 0 volts to the source terminals of the selected and unselected memory cells and to the isolation gates of the selected and unselected memory cells.

5. The method of claim 4, wherein:

the first voltage potential is about 0 volts to 2 volts;

the second voltage potential is about 0.1 volts to 5 volts; and

the third voltage potential is greater than 0 volts but no greater than 2 volts.

6. The method of claim 1, wherein the first voltage potential is about 0 volts to 2 volts.

7. The method of claim 1, wherein the second voltage potential is about 0.1 volts to 5 volts.

8. The method of claim 1, wherein the third voltage potential is greater than 0 volts but no greater than 2 volts.

9. The method of claim 1, wherein:

the first voltage potential is about 0 volts to 2 volts;

the second voltage potential is about 0.1 volts to 5 volts; and

the third voltage potential is greater than 0 volts but no greater than 2 volts.

10. The method of claim 9, wherein:

applying about 0 volts to the source terminals for the selected and unselected memory cells and to the isolation gate of the unselected memory cell; and

applying about a V_DD potential to the isolation gate of the selected memory cell.

11. The method of claim 1, further comprising the step of determining a current passing through the floating gate transistor of the selected memory cell.

12. The method of claim 1, further comprising steps of:

applying a fourth voltage potential to the gate terminal of the isolation transistor of the selected memory cell; and

applying a fifth voltage potential to the gate terminal of the isolation transistor of the unselected memory cell, wherein the fourth voltage potential is higher than the fifth voltage potential.