Testing and repair of wide I/O semiconductor memory devices designed for testing

• US 5,706,234 A
• Filed: 12/13/1996
• Issued: 01/06/1998
• Est. Priority Date: 04/29/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Komai, Yutaka, Perrin, Carl W., Pilch, Charles J. Jr., Smith, Scott E., Le, Duy-Loan T.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): LE, VU ANH
• Application Number:
  US08/766,705
• Time in Patent Office: 389 Days
• Field of Search: 365/201, 365/189.01, 365/189.07, 365/230.03, 365/200, 371/21.1, 371/21.2, 371/21.3
• US Class Current: 365/201
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

A semiconductor memory device 40 includes an array of storage cells 130, addressable by row and column and specifically designed for testing. Row and column addresses are decoded to access a row and plural columns simultaneously. A test data bit to be written into the storage cells is replicated and stored into as many storage cells at once as there are columns simultaneously accessed. Upon readout for a comparison test, plural occurrences of the stored test data bit are compared with each other and with an expected data bit within parallel comparator circuitry 140 located within the memory device. A pass/fail signal (on lead 170) from the parallel comparator circuitry is transmitted to the memory device tester 30 for final defect analysis and correction. When a failure/defect is detected, information representing the address and the type of failure are stored in the memory device tester. A memory device test method also is described.

Claims

1. A memory device comprising:

an array of memory cells arranged in rows and columns;

a row decoder circuit for selecting a first row of memory cells in the array, responsive to a first address;

a column decoder circuit for selecting a first and a second column of memory cells in the array, responsive to a second address and a first logic state of a test mode signal, the column decoder circuit for selecting the first and not the second column of memory cells, responsive to the second address and a second logic state of the test mode signal, and the column decoder circuit for replacing the first and second columns of memory cells, responsive to the second address, if either column of memory cells is defective;

a data terminal of the memory device for receiving a data bit; and

a replicating circuit coupled to the data terminal, responsive to the test mode signal and a write signal, for replicating the data bit into a group of data bits and coupling the group of data bits to selected memory cells in the first and second columns of memory cells of the array.

2. A memory device, in accordance with claim 1, further comprising:

a first sub-array of memory cells in the array of memory cells including the first row of memory cells; and

a second sub-array of memory cells in the array of memory cells, separate from the first sub-array of memory cells, the second sub-array of memory cells including a second row of memory cells,

wherein the row decoder circuit further selects the second row of memory cells, responsive to the first address and the first logic state of the test mode signal, the row decoder circuit replacing the first and second rows of memory cells, responsive to the first address, if either the first or second row of memory cells is defective.

3. A memory device, in accordance with claim 2, wherein the first address is a row address and the second address is a column address.

4. A memory device, in accordance with claim 2, wherein the first column of memory cells is in the first sub-array of memory cells and the second column of memory cells is in the second sub-array of memory cells.

5. A memory device, in accordance with claim 4, wherein the first address comprises a row address and the second address comprises a column address.

6. A memory device, in accordance with claim 2, further comprising plural sets of sub-arrays of memory cells, one of the sets having the first sub-array of memory cells and the second sub-array of memory cells.

7. A memory device, in accordance with claim 6, wherein the first sub-array includes the first column of memory cells, and the second sub-array includes the second column of memory cells.

8. A memory device, in accordance with claim 2, further comprising plural sets of sub-arrays of memory cells, one of the sets having the first sub-array of memory cells and another of the sets having the second sub-array of memory cells.

9. A memory device, in accordance with claim 8, wherein the first sub-array includes the first and the second columns of memory cells.

10. A memory device, in accordance with claim 2, wherein the row decoder circuit comprises plural row decoder circuits and at least one redundant row decoder circuit.

11. A memory device, in accordance with claim 10, wherein the column decoder circuit comprises plural column decoder circuits and at least one redundant column decoder circuit.

12. A memory device, in accordance with claim 11, further comprising a first group of data terminals and a second group of data terminals, wherein only the first group of data terminals is active, responsive to the first logic state of the test mode signal, and the first and second groups of data terminals are active, responsive to the second logic state of the test mode signal.

13. A memory device comprising:

an array of memory cells arranged in rows and columns;

a row decoder circuit for selecting a first row of memory cells in the array, responsive to a first address;

a column decoder circuit for selecting a first and a second column of memory cells in the array, responsive to a second address and a first logic state of a test mode signal, the column decoder circuit for selecting the first and not the second column of memory cells, responsive to the second address and a second logic state of a test mode signal, and the column decoder circuit for replacing the first and second columns of memory cells, responsive to the second address, if either column of memory cells is defective;

a comparison circuit, responsive to the first logic state of the test mode signal and a read signal, for comparing a data bit from the first column of memory cells with another data bit from the second column of memory cells and producing a comparison signal indicating the result of the comparison; and

a data terminal of the device for receiving the comparison signal.

14. A memory device, in accordance with claim 13, wherein the comparison signal is equivalent to the data bits if the data bits are the same, and the comparison signal is not equivalent to the data bits if the data bits are not the same.

15. A memory device, in accordance with claim 14, further comprising:

a latch circuit for storing a test data bit, wherein the comparison circuit further compares the data bits from the selected memory cells with the test data bit for producing the comparison signal.

16. A memory device, in accordance with claim 13, further comprising:

a first sub-array of memory cells in the array of memory cells including the first row of memory cells;

a second sub-array of memory cells in the array of memory cells, separate from the first sub-array of memory cells, the second sub-array of memory cells including a second row of memory cells,

wherein the row decoder circuit further selects the second row of memory cells, responsive to the first address and the first logic state of the test mode signal, the row decoder circuit replacing the first and second rows of memory cells, responsive to the first address, if either the first or second row of memory cells is defective.

17. A memory device, in accordance with claim 16, wherein the first address is a row address and the second address is a column address.

18. A memory device, in accordance with claim 16, further comprising plural sets of sub-arrays of memory cells, one of the sets having the first sub-array of memory cells and the second sub-array of memory cells.

19. A memory device, in accordance with claim 18, wherein the first column of memory cells is in the first sub-array of memory cells, and the second column of memory cells is in the second sub-array of memory cells.

20. A memory device, in accordance with claim 16, further comprising plural sets of sub-arrays of memory cells, one of the sets having the first sub-array of memory cells and another of the sets having the second sub-array of memory cells.

21. A memory device, in accordance with claim 20, wherein the first sub-array includes the first and the second columns of memory cells.

22. A memory device, in accordance with claim 16, wherein the row decoder circuit comprises plural row decoder circuits and at least one redundant row decoder circuit.

23. A memory device, in accordance with claim 22, wherein the column decoder circuit comprises plural column decoder circuits and at least one redundant column decoder circuit.

24. A memory device, in accordance with claim 23, further comprising a first group of data terminals and a second group of data terminals, wherein only the first group of data terminals is active, responsive to the first logic state of the test mode signal, and the first and second groups of data terminals are active, responsive to the second logic state of the test mode signal.

25. A memory device comprising:

a plurality data terminals;

plural sub-arrays of memory cells, each sub-array of memory cells arranged in addressable rows and columns of the memory cells and plural sub-arrays of the memory cells being arranged in sets, each set corresponding to a separate one of the data terminals;

a row decoder circuit, responsive to a row address, for selecting at least one row of memory cells in each of the sets of sub-arrays at once;

a column decoder circuit, responsive to a column address, for selecting a plurality of columns of the memory cells in each of the sets of sub-arrays at once; and

a data comparison circuit for comparing a plurality of data bits from each set of sub-arrays, responsive to a test mode signal, the data comparison circuit producing a pass signal at each data terminal corresponding to a set of sub-arrays wherein the plurality of data bits are the same, the data comparison circuit producing a fail signal at each data terminal corresponding to a set of sub-arrays wherein the plurality of data bits are not the same,

wherein the column decoder circuit is arranged for replacing the plurality of columns of the memory cells with an equal number of columns of redundant memory cells, responsive to the column address, in at least one of the sets of sub-arrays that produced the fail signal.

26. A memory device as in claim 25, wherein the row decoder circuit is arranged for replacing the plurality of rows of the memory cells with an equal number of rows of redundant memory cells, responsive to the row address, in at least one of the sets of sub-arrays that produced the fail signal.

27. A memory device as in claim 26, wherein each set of sub-arrays is a quadrant of sub-arrays.

28. A memory device as in claim 26, wherein the memory cells are dynamic random access memory cells.

29. A memory device as in claim 28, further comprising:

a plurality of input/output buffer circuits, each input/output buffer circuit corresponding to one of the plurality of data terminals, each input/output buffer storing a test data bit, responsive to the test mode signal,

wherein the data comparison circuit further compares the plurality of data bits from each set of sub-arrays with the test data bit stored in the respective each input/output buffer circuit.

30. A method of testing and repairing a semiconductor memory device comprising the steps of:

providing a plurality of semiconductor memory devices, each semiconductor memory device arranged in rows and columns of memory cells and having a plurality of data terminals;

providing memory tester having a plurality of data terminals;

coupling each of the plurality of data terminals of each semiconductor memory device to a separate one of the memory tester data terminals;

applying a test mode signal to the plurality of semiconductor memory devices, thereby initiating a test mode;

applying a write signal, an address signal and a plurality of data bits to each of the plurality of semiconductor memory devices at the same time, each of the plurality of semiconductor memory devices replicating the plurality of data bits in a number of memory cells greater than the plurality of data terminals of the each semiconductor memory device;

applying a read signal and the address signal to the plurality of semiconductor memory devices at the same time, each of the plurality of semiconductor memory devices comparing the data bits from the number of memory cells and producing a pass or fail signal at each of the respective data terminals;

storing the address and an identity of each data terminal corresponding to each fail signal in the memory tester;

determining whether a defective group of memory cells corresponding to the each stored fail signal is a defective row or column of memory cells;

repairing the defective group of memory cells in at least one of the plurality of semiconductor memory devices corresponding to the address and the identity of each data terminal by replacing every group of memory cells corresponding to the address and the identity of each data terminal with an equal number of redundant memory cells.

31. A method of testing and repairing a semiconductor memory device as in claim 30, further comprising the step of programming a decoder circuit in the at least one of the plurality of semiconductor memory devices for replacing the every group of memory cells corresponding to the address and an identity of each data terminal with an equal number of redundant memory cells.

32. A method of testing and repairing a semiconductor memory device as in claim 31, further comprising the step of programming the decoder circuit by blowing a plurality of fuses corresponding to the address of the defective group of memory cells.

33. A method of testing and repairing a semiconductor memory device as in claim 31, further comprising the step of comparing the replicated data bits from each of the plurality of data bits by a logical AND of each of a true and a complement of each of the replicated data bits, thereby producing a plurality of equivalent bits, each equivalent bit corresponding to one of the plurality of data terminals.

34. A method of testing and repairing a semiconductor memory device as in claim 33, further comprising the step of storing a plurality test data bits in a plurality of input/output buffer circuits, each input/output buffer circuit corresponding to one of the plurality of data terminals.

35. A method of testing and repairing a semiconductor memory device as in claim 34, further comprising the step of comparing each equivalent data bit to each respective test data bit.