Self-enabling pulse-trapping circuit

• US 5,706,247 A
• Filed: 11/21/1996
• Issued: 01/06/1998
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Merritt, Todd, Williams, Brett
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/754,308
• Time in Patent Office: 411 Days
• Field of Search: 365/233.5, 365/233, 365/230.08
• US Class Current: 365/233.5
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additional memory addresses. An external input is used to terminate and change a burst operation. Circuitry is provided to monitor the external input during burst operations and provide an appropriate control signal.

Claims

1. An integrated memory device comprising:

a control signal input for receiving a control signal;

an address latch input for receiving an address latch signal; and

a signal trapping circuit coupled to the control signal input and the address latch input and adapted to latch a transition in the control signal.

2. An integrated memory device comprising:

a control signal input for receiving a control signal;

an address latch input for receiving an address latch signal; and

a signal trapping circuit coupled to the control signal input and the address latch input and adapted to latch a transition in the control signal, wherein the signal trapping circuit comprises a high transition latch circuit to latch a low to high transition in the control signal when the address latch signal is activated, the high transition latch circuit comprises;

a first flip-flop circuit having first and second inputs, and an output, the first input is coupled to the control signal input,

a first logic gate having a first input connected to the output of the first flip-flop circuit, a second input connected to the address latch input, and an output;

a second flip-flop circuit having a first input connected to the output of the first logic gate, a second input, and first and second outputs;

a second logic gate having an output connected to the second input of the second flip-flop circuit, a first input connected to the output of the first logic gate, and a second input connected to the address latch input;

a feedback circuit connected to the first output of the second flip-flop circuit and the second input of the first flip-flop circuit; and

an output circuit connected to the first and second outputs of the second flip-flop circuit.

3. The integrated memory of claim 2 further comprising:

a filter circuit coupled to the first flip-flop circuit for filtering a high pulse in the control signal which has a duration less than a predetermine time.

4. The integrated memory of claim 3 wherein the filter circuit is a delay element.

5. The integrated memory of claim 2 wherein the first and second logic gates are NAND gates.

6. The integrated memory of claim 2 wherein the first flip-flop circuit comprises cross coupled NOR gates.

7. The integrated memory of claim 2 wherein the second flip-flop circuit comprises cross coupled NAND gates.

8. The integrated memory of claim 2 wherein the output circuit comprises:

a NAND gate having a first input coupled through a delay circuit to the first output of the second flip-flop circuit, and a second input connected to the second output of the second flip-flop circuit.

9. An integrated memory device comprising:

a control signal input for receiving a control signal;

an address latch input for receiving an address latch signal; and

a signal trapping circuit coupled to the control signal input and the address latch input and adapted to latch a transition in the control signal, wherein the signal trapping circuit comprises a low transition latch circuit to latch a high to low transition in the control signal when the address latch signal is activated, the low transition latch circuit comprises;

a first flip-flop circuit having first and second inputs, and an output, the first input is coupled to the control signal input,

a first logic gate having a first input connected to the output of the first flip-flop circuit, a second input connected to the address latch input, and an output;

a second flip-flop circuit having a first input connected to the output of the first logic gate, a second input, and first and second outputs;

a second logic gate having an output connected to the second input of the second flip-flop circuit, a first input connected to the output of the first logic gate, and a second input connected to the address latch input;

a feedback circuit connected to the first output of the second flip-flop circuit and the second input of the first flip-flop circuit; and

an output circuit connected to the first and second outputs of the second flip-flop circuit.

10. The integrated memory of claim 9 further comprising:

a filter circuit coupled to the first flip-flop circuit for filtering a low pulse in the control signal which has a duration less than a predetermine time.

11. The integrated memory of claim 10 wherein the filter circuit is a delay element.

12. The integrated memory of claim 9 wherein the first and second logic gates are NAND gates.

13. The integrated memory of claim 9 wherein the first flip-flop circuit comprises cross coupled NAND gates.

14. The integrated memory of claim 9 wherein the second flip-flop circuit comprises cross coupled NAND gates.

15. The integrated memory of claim 9 wherein the output circuit comprises:

a NAND gate having a first input coupled through a delay circuit to the second output of the second flip-flop circuit, and a second input connected to the first output of the second flip-flop circuit.

16. A method of latching a control signal in a memory circuit having control signal input and an address latch input, the method comprising the steps of:

receiving an address latch signal on the address latch input;

receiving a control signal on the control signal input;

enabling a latch circuit in response to an active transition of the address latch signal; and

latching a transition of the control signal.

17. The method of claim 16 further including the step of:

producing an output signal in response to the transition of the control signal.

18. The method of claim 16 where in the control signal is a write enable signal.