Semiconductor neural circuit device

• US 5,706,403 A
• Filed: 04/24/1995
• Issued: 01/06/1998
• Est. Priority Date: 10/29/1992
• Status: Expired due to Fees

• Current Assignee: Tadahiro Ohmi, Tadashi Shibata
• Original Assignee: Tadahiro Ohmi, Tadashi Shibata
• Inventors: Shibata, Tadashi, Ohmi, Tadahiro
• Primary Examiner(s): Downs, Robert W.
• Application Number:
  US08/424,267
• Time in Patent Office: 988 Days
• Field of Search: 395/23, 395/24, 395/27
• US Class Current: 706/25
• CPC Class Codes: G06N 3/065 Analogue means

Abstract

A semiconductor neural circuit device having a very simple circuit and a self-teaching function, by which a neural network is allowed to learn. The device comprises synapse circuits which output weighted values, and neuron circuits which execute linear addition of the output signals from the synapse circuits, and output the signal voltages of high and low levels with respect to a given threshold value V_TH. In the case of learning of increasing the total value Z, only when V_TH -ε<Z<V_TH +α with respect to two positive parameters ε and α, the weighted value of predetermined synapse circuits which input signals to the neuron circuit is increased by a given positive value. Conversely, in the case of learning of the decreasing the total value Z, only when the V_TH -α<Z<V_TH +ε, the weighted value of predetermined synapse circuit which input signals to the neuron circuit is decreased by a given positive value.

Claims

1. An artificial neural circuit comprising:

a first plurality of synapse circuits which output values of input signals multiplied by predetermined weighting values W_i, and a plurality of neuron circuits which determine a total value Z representing the result of linear addition of outputted value signals of a second plurality of synapse circuits, and which output a high level signal voltage when, with respect to a predetermined threshold V_TH, Z>

V_TH, and output a low level signal voltage when Z <

V_TH,

wherein during learning of a respective neuron circuit, with respect to learning of increasing the total value Z, only when

space="preserve" listing-type="equation">V.sub.TH -ε

<

Z<

V.sub.TH +α

with respect to two positive parameters ε and

α

is the weighting value of predetermined synapse circuits which input signals into said respective neuron circuit increased by a first predetermined positive value, and

in the case of learning of decreasing the total value Z, only in the case in which

space="preserve" listing-type="equation">V.sub.TH -α

<

Z<

V.sub.TH +ε

is the weighting value of predetermined synapse circuits which input signals into said respective neuron circuit decreased by a second predetermined positive value.

2. An artificial neural circuit in accordance with claim 1, wherein ε

>

α

.

3. An artificial neural circuit in accordance with claim 1, wherein said respective neuron circuit comprises neuron MOS transistors, each neuron MOS transistor having semiconducting regions of a single conductivity type on a substrate, a source region and a drain region of opposite conductivity type provided within said semiconducting regions, a floating gate electrode which is provided in a region between said source region and said drain region via a first insulating film and which has a floating gate potential, and a plurality of control gate electrodes which are capacitively coupled with said floating gate electrode via a second insulating film.

4. An artificial neural circuit in accordance with claim 3, wherein a source follower circuit employing neuron MOS develops a signal from the floating gate potentials of the neuron MOS transistors comprising said respective neuron circuit, said signal being inputted into a circuit which controls the learning of said respective neuron circuit.

5. An artificial neural circuit in accordance with claim 4, wherein at least one of said neuron MOS transistors has a second floating gate electrode disposed perpendicularly to the first-named floating gate electrode of the neuron MOS transistors comprising said respective neuron circuit, said second floating gate electrode and an output terminal of each of said synapse circuits being coupled via capacitance.

6. An artificial neural circuit in accordance with claim 5, wherein a switch for connecting said second floating gate electrode to an electrode possessing a predetermined potential is provided between said second floating gate electrode and said electrode.