Mechanism for receiving messages at a coupling facility

• US 5,706,432 A
• Filed: 06/07/1995
• Issued: 01/06/1998
• Est. Priority Date: 11/04/1993
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Elko, David Arlen, Goss, Steven Neil, Williams, Joseph Arthur, Gregg, Thomas Anthony, Goldrian, Gottfried Andreas, Helffrich, Audrey Ann
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Winder, Patrice L.
• Application Number:
  US08/474,574
• Time in Patent Office: 944 Days
• Field of Search: 395/200.01, 395/200.02, 395/200.08, 395/200.13, 395/849, 395/884
• US Class Current: 709/213
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

Computer system processing complexes which can operate actually or apparently synchronously and in parallel or asynchronously in a network have a coupling facility for sending and receiving commands, responses, and data. The memory for the central processing complexes (which is accessible to each of the processing elements) is provided with storage for messages and data for coupling over a communication channel interface. Each of a plurality of processing elements (CPC) has data objects used to maintain state information for shared data in the coupling facility storage. The coupling facility can receive both message commands and data, sending data and responses to messages, and sending and receiving secondary messages. The processing element accessible memory provides a state information buffer control information operation memory block for describing the hardware communication environment associated with the computer system mechanism for storage of state information pertaining to a communications buffer residing in said coupling facility storage. The communication channel has a set of address registers. The system employs four new instructions, PREPARE CHANNEL BUFFER, SIGNAL CHANNEL BUFFER, MOVE CHANNEL BUFFER DATA, and TEST CHANNEL BUFFER, to enable a coupling facility control program to directly manipulate the address registers and control the flow of data, commands and responses between the coupling-facility storage and communication channels for the central processing elements. This provides a direct interface between the coupling facility and an intersystem communication channel for the receipt of messages and data and the related receiving functions.

Claims

1. A computer system mechanism, comprising:

a coupling facility for providing a central data storage as well as a bidirectional control and data exchange pathway between a plurality of independent central processing units (CPUs) operating externally of said coupling facility,

each one of said plurality of independent CPUs having a main memory, an operating system, and a communications interface form communicating with the coupling facility via an intersystem channel,

said coupling facility including within said coupling facility, a plurality of separate coupling facility processors, a plurality of intersystem channels, interfaces for communicating with said plurality of independent CPUs, a coupling facility storage device for storing shared data which may be concurrently and commonly accessed by said plurality of independent CPUs operating externally of said coupling facility, and wherein any of said plurality of independent CPUs may store data in said coupling facility storage device and wherein said stored data may be retrieved by any of said plurality of independent CPUs including any of said plurality of independent CPUs which originally stored said stored data in said coupling facility storage device, a coupling facility memory interface between the coupling facility storage device and said plurality of intersystem channels, and a coupling facility control program for coupling said intersystem channels to said coupling facility storage device over said coupling facility memory interface,

said coupling facility storing messages commands and data for coupling a particular intersystem channel and the coupling facility processors, each of which has data objects used to maintain state information for the shared data in the coupling facility storage device, said coupling facility memory interface having means for receiving primary message commands and data from any of said plurality of independent CPUs, for sending data and responses to the primary message commands, for sending secondary message commands originated by the coupling facility, triggered by the primary message commands, and for receiving responses to the secondary message commands from the plurality of independent CPUs,

said coupling facility including a state information buffer control information operation memory block within said coupling facility storage device for describing a hardware communication environment associated with the computer system mechanism for storage of state information pertaining to communications buffers residing in said coupling facility memory interface, a set of address registers for said coupling facility memory interface, and wherein is employed, four instructions, PREPARE CHANNEL BUFFER, SIGNAL CHANNEL BUFFER, MOVE CHANNEL BUFFER DATA, and TEST CHANNEL BUFFER, for enabling said coupling facility control program to directly manipulate the address registers and control the flow of the data, message commands and responses directly between the coupling facility storage device and the plurality of independent CPUs.

2. A computer system mechanism according to claim 1, wherein said coupling facility memory interface provides a direct interface between the coupling facility processors, the coupling facility storage device and an intersystem channel for the sending and receipt of message commands, responses, and data.

3. A computer system mechanism according to claim 1 wherein a message command is moved by the coupling facility storage device interface directly into the coupling facility memory.

4. A computer system mechanism according to claim 1 wherein a response to a secondary message command is discarded by an intersystem channel following a signalling of the secondary message command'"'"'s completion.

5. A computer system mechanism according to claim 1 wherein execution of a write command by a CPU is enabled to begin prior to the arrival of any data for a write command, or correspondingly, any data on a read command is allowed to begin transfer on a link to a CPU prior to sending a response.

6. A computer system mechanism according to claim 1 wherein said coupling facility specifies an address for data in a storage structure directly to allow data transfer to be accomplished without the need of a second movement of the data within coupling facility storage device.

7. A computer system mechanism according to claim 1 wherein said coupling facility specifies an address for data in a storage structure accessible to one of the CPUs directly to allow a data transfer to be accomplished without the need of a second movement of the data within coupling facility storage device.

8. A computer system mechanism according to claim 1 further comprising,

an operating system control program for each of said CPUs, and

a coupling facility memory interface for interconnecting said CPUs and said coupling facility storage device for said state information buffer control information operation memory block for describing the hardware communication environment.

9. A computer system mechanism according to claim 1 further comprising,

an operating system control program for each of said CPUs, and

a coupling facility memory interface for interconnecting said CPUs and said coupling facility storage device for said state information buffer control information operation memory block for describing the hardware communication environment, including a memory bus adapter and coupling facility channel bus adapters to which are coupled one or more channel busses to which are linked one or more intersystem channels.

10. A computer system mechanism according to claim 1 wherein said state information buffer control information operation memory block for describing the hardware communication environment stores the location of registers in said coupling facility storage device used to send and receive message commands, and where said coupling facility memory interface includes a plurality of registers used to send and receive message commands, and wherein said PREPARE CHANNEL BUFFER instruction is employed for preparing the transmission of message commands.

11. A computer system mechanism according to claim 1 wherein said PREPARE CHANNEL BUFFER instruction includes a validity field, a field indicating whether the instruction is for a primary or secondary message command, and a channel path field which identifies the associated channel by number, and a base address which points to a location in the state information buffer control information operation memory block within the coupling facility storage device accessible to a CPU.

12. A computer system mechanism according to claim 1 wherein said MOVE CHANNEL BUFFER DATA instruction utilizes a specified coupling facility storage device location as a staging area for movement of data between a channel buffer and an expanded storage.

13. A computer system mechanism according to claim 1 wherein said coupling facility memory interface has a memory bus adapter which includes an active vector and an error state pending vector for association which each intersystem channel.

14. A computer system mechanism according to claim 1 wherein said intersystem channel determines a location of a physical address for message command storage without program intervention.

15. A computer system mechanism according to claim 1 wherein a program run by one of said coupling facility processors detects a command activity originating with an intersystem channel, and builds a response and moves a response onto the intersystem channel with a SIGNAL CHANNEL BUFFER instruction.

16. A computer system mechanism according to claim 1 wherein a program run by one of said coupling facility processors detects data activity originating with an intersystem channel and a secondary message channel instruction is employed.

17. A computer system mechanism according to claim 1 wherein a primary message command employs a primary channel buffer and when a command arrives at the coupling facility a response is sent as an answer.

18. A computer system mechanism according to claim 1 wherein a primary message command employs a primary channel buffer and when a message command arrives at the coupling facility a responses is sent as an answer, and when data may be associated with a message command and when data is associated with a message command the message command is a write, and data may be associated with a response for a primary message command and when data is associated with a response the response is a read.

19. A computer system mechanism according to claim 1 wherein a secondary channel buffer of the coupling facility issues a secondary message command on a secondary buffer and receives a response issued by means of a SIGNAL CHANNEL BUFFER instruction.

20. A computer system mechanism according to claim 1 wherein a command for discard contains an indicator field indicating that a response is to be discarded, which causes the coupling facility to acknowledge the command and discard the response.

21. A computer system mechanism according to claim 1 wherein when an error is detected as occurring on link for said coupling facility memory interface, a retry request is made, and an instruction reissued to retry the link.

22. A computer system mechanism according to claim 1 wherein when an error occurs all command initiation on all coupling facility processors is suspended until the subsequent issuance of a sequence of instructions for a TEST CHANNEL BUFFER operation.

23. A computer system mechanism according to claim 1 wherein upon receipt of a message command a coupling facility processor scans the coupling facility storage device for intersystem channel activity and any next work to be performed, and when the work is assumed by the coupling facility processor the work is isolated to the coupling facility processor.

24. A computer system mechanism according to claim 1 wherein when the SIGNAL CHANNEL BUFFER instruction detects a status pending in the state information buffer control information operation memory block the response is discarded.