Data processing system and method thereof

• US 5,706,488 A
• Filed: 03/01/1995
• Issued: 01/06/1998
• Est. Priority Date: 03/31/1993
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Osborn, Stephen G., Gallup, Michael G., Goke, L. Rodney
• Primary Examiner(s): Treat, William M.
• Application Number:
  US08/398,222
• Time in Patent Office: 1,042 Days
• Field of Search: 395/375, 395/800, 395/564, 364/269
• US Class Current: 712/223
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Claims

1. A method for executing an instruction in a data processor, comprising the steps of:

receiving the instruction;

decoding the instruction to provide a plurality of control signals;

accessing a first digital data value from a first storage location;

accessing a second digital data value from a second storage location;

comparing the second digital data value and the first digital data value to determine and select one of a greater value and a lesser value;

storing the one of the greater value and the lesser value in a destination storage circuit;

accessing a first extension bit and a second extension bit from a storage location, the first extension bit and the second extension bit indicating a previous result of a data processing operation executed prior to receipt of the instruction;

using the first extension bit and the second extension bit to selectively enable comparison means to execute the step of comparing; and

selectively modifying the first extension bit and the second extension bit in response to a result of the step of comparing.

2. The method of claim 1 wherein the step of comparing further comprises the steps of:

subtracting the second digital data value from the first digital data value to generate a subtraction result;

asserting a borrow value if the subtraction result is a negative value; and

negating the borrow value if the subtraction result is a positive value.

3. The method of claim 2 wherein the second digital data value and the first digital data value are compared to determine and select the lesser value in response to execution of the instruction.

4. The method of claim 3 further comprising the step of:

storing the second digital data value in the destination storage circuit when the borrow value is negated.

5. The method of claim 4 wherein the destination storage circuit is the first storage location.

6. The method of claim 2 wherein the second digital data value and the first digital data value are compared to determine and select the greater value in response to execution of the instruction.

7. The method of claim 6 further comprising the step of:

storing the second digital data value in the destination storage circuit when the borrow value is asserted.

8. The method of claim 1 wherein both the first digital data value and the second digital data value are one of a signed data value and an unsigned data value.

9. The method of claim 1 wherein the first digital data value is a first scalar value and the second digital data value is a second scalar value.

10. The method of claim 1 wherein the first digital data value is a portion of a first vector value and the second digital data value is a corresponding portion of a second vector value.

11. The method of claim 1 wherein the first extension bit and the second extension bit collectively represent a plurality of status states of the data processor, wherein:

the first extension bit and the second extension bit are in a default state in a first status state;

the first extension bit and the second extension bit indicate that the second digital data value is less than the first digital data value when the first extension bit and the second extension bit are in a second status state;

the first extension bit and the second extension bit indicate that the second digital data value is greater than the first digital data value when the first extension bit and the second extension bit are in a third status state; and

the first extension bit and the second extension bit indicate that the second digital data value is equal to the first digital data value when the first extension bit and the second extension bit are in a fourth status state.

12. The method of claim 11 further comprising the steps of:

enabling the comparison means to execute the step of comparing when the first extension bit and the second extension bit are in one of the first status state and the fourth status state.

13. The method of claim 11 wherein the first extension bit and the second extension bit indicate that the first digital data value is a most significant byte of a first multi-byte data value and the second digital data value is a most significant byte of a second multi-byte data value when the first extension bit and the second extension bit are in the first status state.

14. The method of claim 11 wherein the first extension bit and the second extension bit indicate that the data processing operation was executed in response to a prior instruction which compared two equal data values when the first extension bit and the second extension bit are in the fourth status state.

15. The method of claim 11 wherein the instruction is one of a preliminary instruction and a non-preliminary instruction, the preliminary instruction modifying both the first extension bit and the second extension bit to reflect the result of the step of comparing, the non-preliminary instruction modifying the first extension bit and the second extension bit to be in the default state.

16. The method of claim 15 further comprising the steps of:

negating the first extension bit and asserting the second extension bit when the first extension bit and the second extension bit are in the second status state;

asserting the first extension bit and negating the second extension bit when the first extension bit and the second extension bit are in the third status state; and

asserting both the first extension bit and the second extension bit when the first extension bit and the second extension bit are in the fourth status state.

17. A data processor, comprising:

an instruction storage circuit for storing an instruction;

a decoder for decoding the instruction to provide a plurality of control signals, the decoder being coupled to the instruction storage circuit for receiving the instruction;

a first storage circuit for storing a first digital data value;

a second storage circuit for storing a second digital data value;

comparison means for comparing the first digital data value and the second digital data value, the comparison means having a first input coupled to the first storage circuit for receiving the first digital data value, the comparison means having a second input for receiving the second digital data value, the comparison means having an output for providing a result which indicates which of the first digital data value and the second digital data value is one of a greater value and a lesser value;

selection means for selectively providing the second digital data value to the first storage circuit when the second digital data value is the one of the greater and the lesser value, the selection means being coupled to the first storage circuit and to the second storage circuit; and

a first control register for storing both a first extension bit and a second extension bit, the first and the second extension bits being used to indicate a status state of the data processor before execution of the instruction.

18. The data processor of claim 17 wherein the comparison means subtracts the second digital data value from the first digital data value to generate the result.

19. The data processor of claim 17 wherein the data processor is in one of a plurality of status states, wherein the plurality of status states comprises:

a first status state to indicate the data processor is in a default state;

a second status state to indicate that the second digital data value is less than the first digital data value;

a third status state to indicate that the second digital data value is greater than the first digital data value; and

a fourth status state to indicate that the second digital data value is equal to the first digital data value.

20. The data processor of claim 17 wherein the selection means provides the second digital data value to the first storage circuit when the instruction determines which of the first digital data value and the second digital data value is the greater value and the data processor is in the third status state.

21. The data processor of claim 17 wherein the selection means provides the second digital data value to the first storage circuit when the instruction determines which of the first digital data value and the second digital data value is the lesser value and the data processor is in the second status state.

22. The data processor of claim 17 wherein the first extension bit and the second extension bit indicate that the first digital data value is a most significant byte of a first multi-byte data value and the second digital data value is a most significant byte of a second multi-byte data value when the data processor is in the first status state.

23. The data processor of claim 17 wherein the first extension bit and the second extension bit indicate that the data processing operation was executed in response to a prior instruction which compared two equal data values when the first extension bit and the second extension bit are in the fourth status state.

24. The data processor of claim 17 further comprising:

a modification circuit coupled to the comparison means for receiving the result and a borrow value corresponding to the result, the modification circuit coupled to the first control register for receiving both the first extension bit and the second extension bit, the modification circuit selectively modifying the first extension bit and the second extension bit.

25. The data processor of claim 24 wherein the instruction is one of a preliminary instruction and a non-preliminary instruction, the preliminary instruction modifying both the first extension bit and the second extension bit to reflect the result of the step of comparing, the non-preliminary instruction modifying the first extension bit and the second extension bit such that the data processor is in the default state.

26. The method of claim 25 wherein the first digital data value is a least significant byte of a first multi-byte value and the second digital data value is a least significant byte of a second multi-byte value during execution of the non-preliminary instruction.

27. The data processor of claim 25 wherein the first extension bit is negated and the second extension bit is asserted when the data processor is in the second status state.

28. The data processor of claim 25 wherein the first extension bit is asserted and the second extension bit is negated when the data processor is in the third status state.

29. The data processor of claim 25 wherein both the first extension bit and the second extension bit are asserted when the data processor is in the fourth status state.

30. The data processor of claim 17 further comprising a control register for storing a sign control value, the sign control value being in a first logic state when the first digital data value and the second digital data value each represent a signed data value, the sign control value being in a second logic state when the first digital data value and the second digital data value each represent an unsigned data value.