Distributed execution of mode mismatched commands in multiprocessor computer systems

• US 5,706,514 A
• Filed: 03/04/1996
• Issued: 01/06/1998
• Est. Priority Date: 03/04/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Bonola, Thomas J.
• Primary Examiner(s): Barry, Lance Leonard
• Application Number:
  US08/610,027
• Time in Patent Office: 673 Days
• Field of Search: 395/200.03, 395/200.05, 395/290, 395/379, 395/670-676, 395/800
• US Class Current: 718/104
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/5044 considering hardware capabilities

Abstract

A technique for handling processor mode mismatched instructions or commands encountered by a CPU within a multiprocessor computer system. During thread execution, if a multimode processor encounters a command or instruction that it cannot execute without shifting modes or mode emulation, it will look for an alternate processor present in the computer system to instead handle the mode mismatched command. If a suitable alternate is found, necessary input parameters including mode reconfiguration information are downloaded to a common memory area accessible to all processors in the system, and the alternate processor is loaded with the starting address of the code that will handle the mismatched command/instruction. The originating processor may suspend thread execution until the alternate processor completes execution. When complete, the alternate processor downloads the results to common memory, and signals its status to the originating processor. Thereafter, the originating processor uploads the results and resumes thread execution if previously suspended.

Claims

1. A method for operating a muliprocessor system, the multiprocessor computer system including a multimode first processor capable configured for operations in a first processing mode, a second processor capable of being configured for operations in a second processing mode incompatible with said first processing mode, means for storing a code vector, and means for storing data and command parameters accessible to both said first and second processors, a method for processing said command encountered by said first processor which cannot be executed while said first microprocessor is in said first processing mode, the method comprising the steps of:

said first processor determining whether said second processor is available for processing said command; and

if said second processor is available for processing said command, said first processor offloading said command to said second processor, said offloading steps comprising;

said first processor downloading data and command parameters required for successful processing of said command to said storing means;

said first processor placing a code vector pointing to source code necessary to complete processing of said command in said code vector storing means;

said first processor activating said second processor;

said second processor utilizing said stored data and command parameters and said stored code vector to commence processing of said command;

said second processor storing results obtained from processing said command to said data and command parameters storage means;

said second processor notifying said first processor when said command processing is complete; and

said first processor uploading said stored results for use in a subsequent task when said second processor notification is received.

2. The method of claim 1, further comprising the steps of:

said second processor entering an active state upon completion of said activating step; and

said second processor entering a sleep state upon completion of said notifying step.

3. The method of claim 2, wherein said second processor availability determining step comprises:

said first processor testing whether said second processor is in said sleep state; and

said first processor determining that said second processor is available for processing said command if said second processor is in said sleep state.

4. The method of claim 2, further comprising the step of:

said first processing setting a semaphore stored in said data and command parameter storage means prior to activating said second processor; and

wherein said second processor resets said semaphore stored in said data and command parameter storage means when said second processor notifies said first processor when said command processing is complete.

5. The method of claim 4, wherein said second processor availability determining step comprises the steps of:

said first processor testing whether said second processor is in said sleep state by interrogating said semaphore; and

said first processor determining that said second processor is available for processing said command if said second processor is in said sleep state.

6. The method of claim 1, wherein said command is encountered by said first processor while said first processor is executing a thread.

7. The method of claim 6, further comprising the steps of:

said first processor suspending execution of said thread after said activating step; and

said first processor resuming execution of said thread after said first processor result uploading step.