Test structure and method for performing burn-in testing of a semiconductor product wafer

• US 5,707,881 A
• Filed: 09/03/1996
• Issued: 01/13/1998
• Est. Priority Date: 09/03/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lum, Thomas Francis
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/706,888
• Time in Patent Office: 497 Days
• Field of Search: 437/7, 437/8, 437/51, 437/211, 437/226, 148/DIG. 162
• US Class Current: 438/15
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A test structure and test methodology are taught herein wherein a test structure (10) is used to test an entire integrated circuit product wafer (44). The test structure (10) has a backing support wafer (39). A die attach compound (38) is used to attach a plurality of segmented individual test integrated circuits 28-34 to the backing support wafer (39). The plurality of test integrated circuits 28-34 have a top conductive bump layer (26). This conductive bump layer (26) is contacted to a thin film signal distribution layer (14) which contains conductive interconnects, conductive layers, and dielectric layers which route electrical signals as illustrated in FIG. 2 . The layer 14 also conductively connects to bumps (46) on a product wafer (44). In addition, leads (40) are coupled to conductive elements of the layer (14). An external tester is coupled via leads (40) to the integrated circuits (28) and (34) whereby the integrated circuits (28-34) burn-in or test integrated circuits on the product wafer (44) in an efficient and effective manner.

Claims

1. A method for manufacturing a test structure, the method comprising the steps of:

providing a base layer having exposed conductive connection regions;

providing a plurality of segmented integrated circuits wherein the segmented integrated circuits have exposed conductive connection regions;

coupling the plurality of segmented integrated circuits to the base layer wherein the exposed conductive connection regions of the plurality of segmented integrated circuits are electrically coupled to the exposed conductive connection regions of the base layer;

forming a stabilizing layer which mechanically strengthens the plurality of segmented integrated circuits which are coupled to the base layer, wherein the stabilizing layer, plurality of segmented integrated circuits, and base layer now form the test structure; and

using the test structure to stimulate at least one integrated circuit.

2. The method of claim 1 wherein the step of using the test structure further comprises:

coupling the test structure to a silicon product wafer wherein the silicon wafer contains a plurality of product integrated circuits which have exposed conductive connection regions, the exposed conductive connection regions of the plurality of product integrated circuits being coupled to product wafer conductive members on the base layer whereby the plurality of segmented integrated circuits can control stimulation of the plurality of product integrated circuits.

3. The method of claim 2 wherein the step of coupling the test structure comprises:

using the plurality of segmented integrated circuits to perform burn-in operations of the plurality of product integrated circuits at a temperature which is elevated above room temperature.

4. The method of claim 2 wherein the product wafer conductive members are located on a first surface of the base layer and the exposed conductive connection regions are located on a second surface of the base layer wherein the first surface is opposite the second surface.

5. The method of claim 1 wherein the step of using the test structure further comprises:

coupling the base layer to the at least one integrated circuit via conductive bumps.

6. The method of claim 1 wherein the step of forming a stabilizing layer comprises:

attaching a semiconductor wafer to backside portions of the plurality of segmented integrated circuits where the semiconductor wafer functions as the stabilizing layer.

7. The method of claim 6 wherein the step of attaching the semiconductor wafer comprises:

attaching the semiconductor wafer to the plurality of segmented integrated circuits using die attach material.

8. The method of claim 1 wherein the base layer is coupled to the plurality of segmented integrated circuits via conductive bumps and wherein the step of forming a stabilizing layer comprises:

forcing bump underfill material into gaps between the conductive bumps so that the underfill material functions as the stabilizing material.

9. The method of claim 1 wherein the base layer is coupled to the plurality of segmented integrated circuits via conductive bumps and wherein the step of forming a stabilizing layer comprises:

applying fill material into gaps located between segmented integrated circuits which are adjacent to each other after being attached to the base layer, the fill material functioning as the stabilizing material.

10. The method of claim 1 wherein the step of placing the plurality of segmented integrated circuits comprises:

testing each segmented integrated circuit within the plurality of segmented integrated circuits to ensure that each segmented integrated circuit coupled to the base layer is functional before coupling to the base layer takes place.

11. The method of claim 1 further comprising:

attaching conductive leads to the base layer wherein the conductive leads are adapted to be contacted to a external tester whereby the external tester provides electrical signals to the plurality of segmented integrated circuits through the conductive leads.

12. The method of claim 11 further comprising:

forming a lead stabilizing material in contact with the conductive leads to mechanically stabilize the conductive leads.

13. The method of claim 12 wherein the step of forming the lead stabilizing material comprises:

forming the lead stabilizing material as a region of epoxy.

14. The method of claim 1 wherein the step of placing the plurality of segmented integrated circuits comprises:

using conductive bumps to make electrical contact between the placing the plurality of segmented integrated circuits and the base layer.

15. The method of claim 1 wherein the step of providing a base layer comprises:

providing the base layer as a thin film where the thin film contains at least one conductive layer encapsulated by a dielectric material, the at least one conductive layer being used to electrically couple the plurality of segmented integrated circuits to the at least one integrated circuit.

16. The method of claim 15 wherein the step of providing the base layer as a thin film comprises:

forming the thin film on top of a silicon wafer mold.

17. The method of claim 15 wherein the step of providing the base layer as a thin film comprises:

forming the thin film on top of a silicon wafer mold wherein the silicon wafer mold is sacrificial and is removed from the base layer before the step of using the test structure to test at least one integrated circuit is performed.

18. The method of claim 17 wherein the silicon wafer mold is at least partially removed by a polishing process.

19. The method of claim 17 wherein the silicon wafer mold is at least partially removed by a chemical etching process.

20. The method of claim 15 wherein the step of providing the base layer as a thin film comprises:

forming the base layer by depositing and selectively etching a plurality of conductive layers and a plurality of dielectric layers using lithographic processing.

21. The method of claim 1 wherein the stabilizing layer is a wafer coupled to backside of the plurality of segmented integrated circuits and wherein the stabilizing layer, plurality of segmented integrated circuits, and the at least one integrated circuit are formed from materials so that coefficients of thermal expansion of the within the stabilizing layer, plurality of segmented integrated circuits, and the at least one integrated circuit are substantially equivalent.

22. The method of claim 1 further comprising:

performing burn-in operations on the test structure before using the test structure in the step of using the test structure to stimulate at least one integrated circuit.

23. A method for testing product integrated circuits using a test structure:

providing a test structure wherein the test structure is a semiconductor wafer coupled to a plurality of segmented test integrated circuits where the plurality of segmented test integrated circuits are coupled to a signal distribution film;

placing a product wafer containing product integrated circuits in contact with the signal distribution film;

stimulating the product integrated circuits via electrical signals provided from the plurality of segmented test integrated circuits to the product integrated circuits via the signal distribution film;

identifying which product integrated circuits are failing product integration circuits in response to the step of stimulating; and

dicing and packaging for use the product integrated circuits which are not falling product integrated circuits.

24. A method for manufacturing a test structure, the method comprising the steps of:

providing a silicon mold;

forming a dielectric layer on the silicon mold;

forming product wafer contact openings in the first dielectric layer;

forming at least one conductive layer of material overlying the first dielectric layer, the at least one conductive layer forming product wafer contact areas through the product wafer contact openings;

forming additional dielectric layers as are needed to isolate portions of the at least one conductive layer of material;

defining top portions of the at least one conductive layer of material as test structure contact areas;

providing segmented test integrated circuits which have a top layer of conductive bumps and a backside;

attaching segmented test integrated circuits to the test structure contact areas via the conductive bumps of the segmented test integrated circuits;

attaching a support wafer to the backside of each of the segmented test integrated circuits;

attaching conductive leads to conductive lead areas of the at least one conductive layer of material; and

removing the silicon mold to expose the product wafer contact areas so that the segmented test integrated circuits can communicate electrical signals through the at least one conductive layer of material to the product wafer contact areas.

25. The method of claim 24 further comprising:

attaching conductive contacts of a product wafer to the product wafer contact areas; and

testing the product wafer by communicating electrical signals from the segmented test integrated circuits through the at least one conductive layer of material to the product wafer contact areas.

26. The method of claim 25 wherein the step of attaching conductive contacts of a product wafer comprises:

attaching conductive contacts of a product wafer to the product wafer contact areas wherein the conductive contacts of the product wafer are conductive bumps.

27. The method of claim 24 wherein the step of attaching conductive leads comprises:

forming a mechanical support material in contact with the conductive leads after the conductive leads have been coupled to the at least one conductive layer of material.

28. The method of claim 24 wherein the step of attaching segmented test integrated circuits comprises:

applying fill material to fill gaps between the conductive bumps of the segmented test integrated circuits.

29. The method of claim 24 wherein the step of attaching segmented test integrated circuits comprises:

applying fill material to fill gaps between the conductive bumps of the segmented test integrated circuits.

30. The method of claim 24 wherein the step of forming a dielectric layer comprises:

forming the dielectric layer as a polyimide layer.

31. A method for forming a multi-chip module, the method comprising the steps of:

providing a base substrate;

forming transistors and conductive interconnects on top of the substrate the conductive interconnects having top-level contact areas;

contacting conductive members of a singulated integrated circuit to the top-level contact areas so that circuitry on the integrated circuit can electrically communicate with the transistors;

removing a portion of the base substrate to form a remaining base substrate from the base substrate; and

packaging the remaining base substrate, transistors, and singulated integrated circuit in an integrated circuit package which contains conductors that connects to one or more of the singulated integrated circuit or the transistors.

32. The method of claim 31 wherein the step of contacting conductive members comprises:

forming the conductive members as conductive bumps.

33. The method of claim 31 wherein the step of providing a base substrate comprises:

providing the base substrate as a silicon in insulator (SOI) substrate.

34. The method of claim 33 wherein the step of providing a base substrate comprises:

providing the base substrate as a silicon in insulator (SOI) substrate having a top semiconductive region used to form the transistors, a middle dielectric layer, and a bottom base layer underlying the middle dielectric layer.

35. The method of claim 34 wherein the step of removing comprises:

substantially removing the bottom base layer.

36. The method of claim 34 wherein the step of forming transistors and conductive interconnects comprises:

forming conductive interconnects through the top semiconductive region and the middle dielectric layer wherein these conductive interconnects contact at least one of the transistors.

37. The method of claim 31 wherein the step of contacting conductive members of a singulated integrated circuit comprises:

testing the singulated integrated circuit die before the step of contacting.