Bonding pad structure and method thereof

• US 5,707,894 A
• Filed: 10/27/1995
• Issued: 01/13/1998
• Est. Priority Date: 10/27/1995
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsiao, Ming-Shan
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/549,629
• Time in Patent Office: 809 Days
• Field of Search: 437/190, 437/192, 437/194, 437/195, 437/209
• US Class Current: 438/614
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/85424 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A structure and a process for forming an improved bonding pad which resists bond pad peeling of between the bonding pad layer and the underlying layers. The method comprises forming plurality of anchor pads on said substrate surface in a bonding pad area. Next, a first insulating layer is formed over said substrate surface and the anchor pads. Vias are formed through the first insulating layer. The vias are filled with a second metal layer making a connection to the anchor pads and the first insulating layer is covered in the bonding pad area with the second metal layer. It is important that the via holes have a smaller cross sectional area than the anchor pads so that the combination of the anchor pads and the second metal form small "hooks" into the first insulating layer that hold the second metal (bonding pad layer) to the underlying layer.

Claims

1. A method of forming an integrated circuit having an improved bonding pad which resists bonding pad peeling, the method comprising:

providing a substrate having active or passive devices formed therein or thereon and having a substrate surface;

forming a first metal layer over said substrate surface;

masking and etching said first metal layer to form an array of anchor pads on said substrate surface in a bonding pad area;

forming a first insulating layer over said substrate and said array of anchor pads, said anchor pads laterally separated from one another by said first insulating layer;

forming via holes through said first insulating layer to expose surfaces of said anchor pads, said via holes having a smaller cross sectional area than said anchor pads;

filling said via holes with a second metal layer and covering said first insulating layer in said bonding pad area with said second metal layer, said second metal layer making connections to said anchor pads through said via holes.

2. The method of claim 1 which further includes a metal contact to said second metal layer;

and said metal contact is composed of a material selected from the group consisting of;

aluminum and gold.

3. The method of claim 1 wherein said anchor pads have a square shape with a length and a width in the range between about 0.5 to 5.0 μ

m.

4. The method of claim 1 wherein said via holes have a square shape with a length and width in the range between about 0.3 to 5.0 μ

m.

5. The method of claim 1 where said anchor pads have a thickness in the range between about 1000 to 12,000 Å

.

6. The method claim 1 wherein said first insulating layer has a thickness in the range between about 3000 to 20,000 Å

.

7. The method claim 1 wherein said first insulating layer is formed of a material selected from the group consisting of silicon oxide, borophosphosilicate glass (BPSG), and phosphosilicate glass (PSG).

8. The method of claim 1 wherein said second metal layer is formed by forming a via metal layer filling said via holes, and forming a third metal layer overlying the via metal layer.

9. The method of claim 8 wherein said third metal layer has a thickness in the range between about 5000 to 20,000 Å

.

10. The method of claim 8 wherein said second metal layer has a thickness in the range between about 5000 Å

to 15,000 Å

.

11. The method of claim 1 which further includes forming a dielectric layer on the substrate surface, forming a titanium nitride layer on said dielectric layer and forming said second metal layer over said titanium nitride layer.

12. The method of claim 1 wherein said anchor pads are formed of a material selected from the group consisting of:

aluminum, polycide, polysilicon, and a diffusion in said substrate.

13. The method of claim 1 wherein the spacing between adjacent metal pads is in the range between about 0.5 to 10 μ

m.

14. The method of claim 1, wherein said via holes are centered on said anchor pads.

15. A method for forming integrated circuit device including a bonding pad with an anchor structure, the method comprising:

forming a conducting layer over a substrate;

removing a portion of said conducting layer to form first and second individual anchor pads in the conducting layer;

forming a first dielectric layer over and between said first and second individual anchor pads;

forming a first via through said first dielectric layer and contacting said first individual anchor pad, said first via having a smaller cross-sectional area than said first individual anchor pad;

forming a second via through said first dielectric layer and contacting said second individual anchor pad;

said second via having a smaller cross-sectional area than said second individual anchor pad; and

placing conducting material above said first dielectric layer and within said first and second vias to contact said first and second individual anchor pads,

wherein a lower portion of said conducting material contacts said first and second individual anchor pads and an upper portion of said conducting material connects both said first and said second anchor pads to an external contact.

16. The method of claim 15, wherein said conducting material includes two metal layers.

17. The method of claim 15, wherein said vias and anchor pads are formed to be square in shape when viewed from above.

18. The method of claim 15, wherein said anchor pads are square in shape when viewed from perpendicular to said substrate.

19. The method of claim 15, wherein said vias and anchor pads are square in cross section.

20. The method of claim 15, wherein said first via contacts said first anchor pad in a center of said first anchor pad.