Method for adjusting fetch program counter in response to the number of instructions fetched and issued

• US 5,708,788 A
• Filed: 09/05/1995
• Issued: 01/13/1998
• Est. Priority Date: 03/03/1995
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Katsuno, Akira, Savkar, Sunil W., Patkar, Niteen A, Shebanow, Michael C.
• Primary Examiner(s): Lim, Krisna
• Application Number:
  US08/524,294
• Time in Patent Office: 861 Days
• Field of Search: 395/390, 395/561
• US Class Current: 712/214
• CPC Class Codes: G06F 9/321 Program or instruction counter, e.g. incrementing
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks

Abstract

A clocked instruction flow is managed subject to issue and fetch constraints through a plurality of instruction latches which receive instructions from selected memory locations. By checking the number of instructions fetched and issued, the fetch program counter is adjusted responsive to the status of selected state variables indicating instructions issued and fetched. The instruction latches are fully scheduled from cycle to cycle with instructions, by fetching instructions in accordance with a fetch program counter.

Claims

1. A method of managing a clocked instruction flow subject to issue and fetch constraints in plurality of instruction latches which receive instructions, including, from selected memory locations, said method comprising the steps of:

checking whether a taken control transfer instruction is latched for issue;

checking whether a taken control transfer instruction is fetched;

checking whether a fetched taken control transfer instruction will not be in the next issue cycle;

checking whether a taken control transfer instruction is latched for issue in the current cycle;

determining the number of instructions fetched and the number of instructions issued in the current cycle;

adjusting the fetch program counter in relationship to the number of issued instructions and the number of fetched instructions, if there is no taken control transfer instruction being fetched or latched for issue;

adjusting the fetch program counter in relationship to the number of issued instructions and the number of fetched instructions, if no taken control transfer instruction is latched for issue, and a taken control transfer instruction is fetched, or a fetched taken control transfer instruction is not latched for issue;

adjusting the fetch program counter to the target program counter of the first taken branch in the fetch cycle, if there is no taken control transfer instruction in the issue cycle, there is a predict taken branch in the fetch cycle, and there is a predict taken branch in the fetch cycle which will be loaded for issue;

adjusting the fetch program counter to the target program counter of the first taken branch in the issue cycle, if there is a taken control transfer instruction in the issue cycle, and there is a predict taken branch latched for issue which will not be issued in this cycle;

adjusting the fetch program counter to the current cycle fetch program count plus the fetch count, if there is a taken control transfer instruction in the issue cycle but not in the fetch cycle, and a taken control transfer instruction which will be latched for issue; and

adjusting the fetch program counter to the target program counter of the first taken branch in the fetch cycle, if there is a taken control transfer instruction in the issue cycle and in the fetch cycle, and there is a taken control transfer instruction in the issue cycle which will be latched for issue in this cycle.

2. The method according to claim 1 wherein the fetch program counter is adjusted according to the relationship:

FPC_-- D=PC_-- Q+ISSUE_-- CNT+min{EI, NC_-- Q! NV_-- Q+FETCH_-- CNT-ISSUE_-- CNT}, where;

EI=k means the number of issue latch entries, and NV_-- Q is the number of instructions in the issue latch which are valid, i.e., 0<

=nv_-- q<

=k, where k is the number of a particular issue latch entry, wherein, "PC_-- Q" means the current program counter (PC) value in the issue cycle;

"FPC_-- Q" means the fetch program counter value (FPC) in the current cycle;

"FETCH_-- CNT" is the number of instructions which are fetched, i.e., 0<

=FETCH_-- CNT<

=j;

"ISSUE_-- CNT" means the number of instructions which are issued, i.e., 0<

=issue_-- cnt<

=min{i, NV_-- Q}; and

"NV_-- D" is the number of instructions which will be valid in the next cycle.

3. The method according to claim 1 wherein the fetch program counter is adjusted according to the relationship:

FPC_-- D=PC_-- Q+min{EI+ISSUE_-- CNT, NV+Q!NV_-- Q+FETCH_-- CNT}, where;

EI=k means the number of issue latch entries, and NV_-- Q is the number of instructions in the issue latch which are valid, i.e., 0<

=nv_-- q<

=k, where k is the number of issue latch entries, wherein, "PC_-- Q" means the current program counter (PC) value in the issue cycle;

"FPC_-- Q" means the fetch program counter value (FPC) in the current cycle;

"FETCH_-- CNT" is the number of instructions which are fetched, i.e., 0<

=FETCH_-- CNT<

=j;

"ISSUE_-- CNT" means the number of instructions which are issued, i.e., 0<

=issue_-- cnt<

=min{i, NV_-- Q}; and

"NV_-- D" is the number of instructions which will be valid in the next cycle.

6. The method according to claim 3 wherein the fetch program counter is adjusted according to the relationship:

FPC_-- D=PC_-- Q+min{EI+ISSUE_-- CNT, NV+Q!NV_-- Q+FETCH_-- CNT}, where;

EI=k means the number of issue latch entries, and NV_-- Q is the number of instructions in the issue latch which are valid, i.e., 0<

=nv_-- q<

=k, where k is the number of issue latch entries, wherein, "PC_-- Q" means the current program counter (PC) value in the issue cycle;

"FPC_-- Q" means the fetch program counter value (FPC) in the current cycle;

"FETCH_-- CNT" is the number of instructions which are fetched, i.e., 0<

=FETCH_-- CNT<

=j;

"ISSUE_-- CNT" means the number of instructions which are issued, i.e., 0<

=issue_-- cnt<

=min{i, NV_-- Q}; and

"NV_-- D" is the number of instructions which will be valid in the next cycle.

4. A method of managing a clocked instruction flow subject to issue and fetch constraints in plurality of instruction latches which receive instructions, including, from selected memory locations, said method comprising the steps of:

checking whether a taken control transfer instruction is latched for issue;

checking whether a taken control transfer instruction is fetched;

checking whether a fetched taken control transfer instruction will not be in the next issue cycle;

checking whether a taken control transfer instruction is latched for issue in the current cycle;

determining the number of instructions fetched and the number of instructions issued in the current cycle;

adjusting the fetch program counter in relationship to the number of issued instructions and the number of fetched instructions, if there are no taken control transfer instructions being fetched or latched for issue, and a taken control transfer instruction is fetched, or a fetched taken control transfer instruction is not latched for issue;

adjusting the fetch program counter to the target program counter of the first taken branch in the fetch cycle, if there are no taken control transfer instruction being fetched or latched for issue, and a taken control transfer instruction is fetched, or a fetched taken control transfer instruction is latched for issue;

adjusting the fetch program counter to the target program counter of the second taken branch in the issue cycle, if there are no first branch taken control transfer instruction being fetched but there is a second branch taken control transfer instruction being latched for issue;

adjusting the fetch program counter to the target program counter of the first taken branch in the issue cycle, if there is a first taken control transfer instruction in the issue cycle, and the first branch in the issue cycle is not issued in the same cycle;

adjusting the fetch program counter to the current cycle fetch program count plus the fetch count, if there is a taken control transfer instruction in the issue cycle but not in the fetch cycle, and a taken control transfer instruction which will be latched for issue; and

adjusting the fetch program counter to the target program counter of the first taken branch in the fetch cycle, if there is a taken control transfer instruction in the issue cycle and in the fetch cycle, and there is a taken control transfer instruction in the issue cycle which will be latched for issue in this cycle.

5. The method according to claim 4 wherein the fetch program counter is adjusted according to the relationship:

FPC_-- D=PC_-- ISSUE_-- CNT+min{EI, NC_-- Q!NV_-- Q+FETCH_-- CN-ISSUE_-- CNT}, where;

EI=k means the number of issue latch entries, and NV_-- Q is the number of instructions in the issue latch which are valid, i.e., 0<

=nv_-- q<

=k, where k is the number of issue latch entries, wherein, "PC_-- Q" means the current program counter (PC) value in the issue cycle;

"FPC_-- Q" means the fetch program counter value (FPC) in the current cycle;

"FETCH_-- CNT" is the number of instructions which are fetched, i.e., 0<

=FETCH_-- CNT<

=j;

"ISSUE_-- CNT" means the number of instructions which are issued, i.e., 0<

=issue_-- cnt<

=min{i, NV_-- Q}; and

"NV_-- D" is the number of instructions which will be valid in the next cycle.

7. A method of managing a clocked instruction flow subject to issue and fetch constraints in plurality of instruction latches which receive instructions, including, from selected memory locations, said method comprising the steps of:

checking whether a taken control transfer instruction is latched for issue;

checking whether a taken control transfer instruction is fetched;

checking whether a fetched taken control transfer instruction will not be in the next issue cycle;

checking whether a taken control transfer instruction is latched for issue in the current cycle;

determining the number of instructions fetched and the number of instructions issued in the current cycle;

adjusting the fetch program counter in relationship to the number of issued instructions and the number of fetched instruction, if there is no first taken control transfer instruction latched for issue, there is no second taken control transfer instruction latched for issue, and no second taken control transfer instruction is fetched;

adjusting the fetch program counter in relationship to the number of issued instructions and the number of fetched instruction, if there is no first taken control transfer instruction latched for issue, there is no second taken control transfer instruction latched for issue, a second taken control transfer instruction is fetched, and the first control transfer function fetched will not latch to issue;

adjusting the fetch program counter in relationship to the number of issued instructions and the number of fetched instruction, if there is no first taken control transfer instruction latched for issue, there is no second taken control transfer instruction latched for issue, a second taken control transfer instruction is fetched, a first fetched control transfer instruction includes a non-annulled delay instruction not in a fetch cycle, the first control transfer function fetched will latch to issue, and a first fetched control transfer instruction includes a non-annulled delay instruction not in an issue cycle;

adjusting the fetch program counter to the target program counter of the first taken branch in the fetch cycle, if there is no first taken control transfer instruction latched for issue, there is no second taken control transfer instruction latched for issue, a second taken control transfer instruction is fetched, a first fetched control transfer instruction includes a non-annulled delay instruction not in a fetch cycle, the first control transfer function fetched will latch to issue, and a first fetched control transfer instruction includes a non-annulled delay instruction not in an issue cycle;

adjusting the fetch program counter to the target program counter of the first taken branch in the fetch cycle, if there is no first taken control transfer instruction latched for issue, there is no second taken control transfer instruction latched for issue, a second taken control transfer instruction is fetched, and a first fetched control transfer instruction does not include a non-annulled delay instruction not in a fetch cycle;

adjusting the fetch program counter in relationship to the number of issued instructions and the number of fetched instruction, if there is no first taken control transfer instruction latched for issue, there is a second taken control transfer instruction latched for issue, and a second control transfer instruction latched for issue includes a non-annulled delay instruction which will not be issued;

adjusting the fetch program counter to the target program counter of the second taken branch in the issue cycle, if there is no first taken control transfer instruction latched for issue, there is a second taken control transfer instruction latched for issue, and a second control transfer instruction latched for issue does not include a non-annulled delay instruction which will not be issued;

adjusting the fetch program counter in relationship to the number of issued instructions and the number of fetched instruction, if there is a first taken control transfer instruction latched for issue, a first control transfer instruction latched for issue includes a non-annulled delay instruction not latched for issue, or a fetched taken control transfer instruction is not latched for issue;

adjusting the fetch program counter to the target program counter of the first taken branch in the issue cycle, if there is a first taken control transfer instruction latched for issue, a first control transfer instruction latched for issue does not include a non-annulled delay instruction not latched for issue, or a fetched taken control transfer instruction is not latched for issue, and a first control transfer instruction without a delay instruction in the issue cycle is issued in its current cycle or both the first control transfer instruction and the delay instruction which is not annulled, are issued;

adjusting the fetch program counter to the current cycle fetch program count plus the fetch count, if there is a first taken control transfer instruction latched for issue, a first control transfer instruction latched for issue does not include a non-annulled delay instruction not latched for issue, no second taken control transfer instruction is fetched, and a first control transfer instruction without a delay instruction in the issue cycle is issued in its current cycle or both the first control transfer instruction and the delay instruction which is not annulled, are issued;

adjusting the fetch program counter to the current cycle fetch program count plus the fetch count, if there is a first taken control transfer instruction latched for issue, a first control transfer instruction latched for issue does not include a non-annulled delay instruction not latched for issue, a second taken control transfer instruction is fetched, a first fetched control transfer instruction includes a non-annulled delay instruction in a fetch cycle, and a first control transfer instruction without a delay instruction in the issue cycle is issued in its current cycle or both the first control transfer instruction and the delay instruction which is not annulled, are issued; and

adjusting the fetch program counter to the target program counter of the first taken branch in the fetch cycle, if there is a first taken control transfer instruction latched for issue, a first control transfer instruction latched for issue does not include a non-annulled delay instruction not latched for issue, a second taken control transfer instruction is fetched, a first fetched control transfer instruction includes a non-annulled delay instruction not in a fetch cycle; and

a first control transfer instruction without a delay instruction in the issue cycle is issued in its current cycle or both the first control transfer instruction and the delay instruction which is not annulled, are issued.

8. The method according to claim 7 wherein the fetch program counter is adjusted according to the relationship:

FPC_-- D=PC_-- Q+ISSUE_-- CNT+min{EI, NC_-- Q!NV_-- Q+FETCH_-- CN-ISSUE_-- CNT}, where;

EI=k means the number of issue latch entries, and NV_-- Q is the number of instructions in the issue latch which are valid, i.e., 0<

=nv_-- q<

=k, where k is the number of issue latch entries, wherein, "PC_-- Q" means the current program counter (PC) value in the issue cycle;

"FPC_-- Q" means the fetch program counter value (FPC) in the current cycle;

"FETCH_-- CNT" is the number of instructions which are fetched, i.e., 0<

=FETCH_-- CNT<

=j;

"ISSUE_-- CNT" means the number of instructions which are issued, i.e., 0<

=issue_-- cnt<

=min{i, NV_-- Q}; and

"NV_-- D" is the number of instructions which will be valid in the next cycle.

9. The method according to claim 7 wherein the fetch program counter is adjusted according to the relationship:

FPC_-- D=PC_-- Q+min{EI+ISSUE_-- CNT, NV+Q!NV_-- Q+FETCH_-- CNT}, where;

EI=k means the number of issue latch entries, and NV_-- Q is the number of instructions in the issue latch which are valid, i.e., 0<

=nv_-- q<

=k, where k is the number of a particular issue latch entry, wherein, "PC_-- Q" means the current program counter (PC) value in the issue cycle;

"FPC_-- Q" means the fetch program counter value (FPC) in the current cycle;

"FETCH_-- CNT" is the number of instructions which are fetched, i.e., 0<

=FETCH_-- CNT<

=j;

"ISSUE_-- CNT" means the number of instructions which are issued, i.e., 0<

=issue_-- cnt<

=min{i, NV_-- Q}; and

"NV_-- D" is the number of instructions which will be valid in the next cycle.