Process and apparatus for generating power management events in a computer system

• US 5,708,819 A
• Filed: 10/10/1995
• Issued: 01/13/1998
• Est. Priority Date: 10/10/1995
• Status: Expired due to Term

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: Dunnihoo, Jeffrey C.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/541,642
• Time in Patent Office: 826 Days
• Field of Search: 395/750, 364/707, 364/492, 307/38, 307/64, 307/126, 365/226, 365/229
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

A process and apparatus for reducing power consumption in processor-based system by interrupting the main system power supply during periods of inactivity. Existing input/output circuitry is powered from a constant auxiliary power source to monitor system interrupts which are used to generate power events that control the on/off state of the main system power supply.

Claims

1. An apparatus for reducing power consumption in a processor-based system, said apparatus comprising:

means for monitoring a processor-selected plurality of input/output events occurring in said processor-based system and for generating a dedicated power interrupt in response to the occurrence of any of said events;

static logic state means for receiving said dedicated power interrupt and generating an output signal which alternates between a first logic state and a second logic state in response to each occurrence of said dedicated power interrupt; and

a power supply for connection to a power source and having an on state and an off state, said power supply including

means for conveying power from said power source to said processor-based system when said power supply is in said on state and interrupting said power to said processor-based system when said power supply is in said off state, and

means, responsive to said output signal, for placing said power supply in said on state when said output signal is in said first logic state and in said off state when said output signal is in said second logic state.

2. The apparatus of claim 1, wherein

said power supply further includes means for conveying power from said power source to said monitoring means and said static logic state means at all times.

3. The apparatus of claim 1, wherein

said monitoring means and said static logic state means are powered from an auxiliary power source.

4. The apparatus of claim 1, wherein

said static logic state means further comprises reset means for placing said output signal in said first logic state upon initial connection of said power supply to said power source.

5. The apparatus of claim 1 wherein said static logic state means comprises a flip flop.

6. An apparatus for reducing power consumption in a processor-based system, said apparatus comprising:

means for monitoring a processor-selected input/output function of said processor-based system and for generating a block interrupt in response to the occurrence of said function;

interrupt steering means having a first input for receiving said block interrupt, a second input for receiving a control signal, a first output for generating a system interrupt to said processor-based system and a second output for generating a power event signal, the system interrupt being generated upon receipt of said block interrupt when the control signal is in a first control state and said power event signal being generated upon receipt of said block interrupt when the control signal is in a second control state;

static logic state means, responsive to said power event signal, for generating an output signal which alternates between a first logic state and a second logic state in response to each occurrence of said power event signal; and

a power supply for connection to a power source and having an on state and an off state, said power supply including

means for conveying power from said power source to said processor-based system when said power supply is in said on state and interrupting said power to said processor-based system when said power supply is in said off state, and

means, responsive to said output signal, for placing said power supply in said on state when said output signal is in said first logic state and in said off state when said output signal is in said second logic state.

7. The apparatus of claim 6, wherein

said power supply further includes means for conveying power from said power source to said monitoring means, said interrupt steering means and said static logic state means at all times.

8. The apparatus of claim 6, wherein

said monitoring means, said interrupt steering means and said static logic state means are powered from an auxiliary power source.

9. The apparatus of claim 6, wherein said control signal is generated by the processor within said processor-based system.

10. The apparatus of claim 6 wherein said interrupt steering means comprises a multiplexer.

11. The apparatus of claim 6 wherein said static logic state means comprises a flip flop.