Method of making PMOSFETs having indium or gallium doped buried channels and n+ polysilicon gates and CMOS devices fabricated therefrom

• US 5,710,055 A
• Filed: 06/07/1995
• Issued: 01/20/1998
• Est. Priority Date: 12/01/1994
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Kizilyalli, Isik C.
• Primary Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/478,133
• Time in Patent Office: 958 Days
• Field of Search: 437/45, 437/20, 437/41 CS
• US Class Current: 438/289
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Abstract

Sub-micron PMOSFETs including n⁺ polysilicon gates and buried channels having impurity concentrations comprising indium or gallium are provided. The buried channel PMOSFETs have improved short channel characteristics and are particularly suitable for use in CMOS technologies.

Claims

1. A process for making a PMOSFET device comprising the steps of:

a) providing a n-type substrate having a principal surface;

b) forming a channel region having a first end and a second end by implanting indium impurity ions into said principal surface of said substrate;

c) forming a gate oxide layer on the principal surface of said substrate;

d) forming a n⁺ type polysilicon layer on said gate oxide layer;

e) patterning and etching said polysilicon layer to form at least one n⁺ type polysilicon gate electrode on said gate oxide layer; and

f) forming a source region adjacent said first end of said channel region and a drain region adjacent said second end of said channel region by introducing impurity ions into said principal surface of said substrate.

2. The process for making a PMOSFET device according to claim 1, further comprising forming at least one insulator layer on said polysilicon gate electrode.

3. The process for making a PMOSFET device according to claim 1, further comprising forming contact layers on said source region, said drain region and said gate electrode.

4. The process according to claim 1, wherein the step of providing a substrate comprises providing said substrate having a field oxide layer.

5. A process according to claim 1, wherein said step of providing a substrate includes applying a screen layer having a thickness of from about less than 200 angstroms to said substrate.

6. The process according to claim 1, wherein said step of forming said channel region by implanting indium impurity ions comprises implanting said impurity ions at a dose of from about 1×

10¹¹ cm^-2 to about 1×

10¹⁴ cm^-2 at an implantation energy of about less than 100 keV.

7. The process according to claim 1, wherein said step of forming said channel region by implanting indium impurity ions comprises implanting said impurity ions at a dose of about 1.4×

10¹³ cm^-2 at an implantation energy of about 30 keV.

8. The process according to claim 1, wherein said step of forming said channel region comprises forming said channel region having a depth from said principal surface less than about 0.05 μ

m.

9. The process according to claim 8, wherein said step of forming said channel region comprises forming said channel region having a depth from said principal surface of about 0.03 μ

m.