Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells

• US 5,710,072 A
• Filed: 11/18/1996
• Issued: 01/20/1998
• Est. Priority Date: 05/17/1994
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Siemens AG
• Inventors: Risch, Lothar, Krautschneider, Wolfgang, Hofmann, Franz
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US08/737,236
• Time in Patent Office: 428 Days
• Field of Search: 438/268, 438/270, 438/272, 438/237, 438/137, 438/138, 438/156, 438/157, 438/197
• US Class Current: 438/197
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/01 Manufacture or treatment

Abstract

To produce an arrangement containing self-amplifying dynamic MOS transistor memory cells which each comprise a selection transistor, a memory transistor and a diode structure, the selection transistor and the memory transistor being connected in series via a common nodal point and the diode structure being connected between the common nodal point and the gate electrode (10) of the memory transistor, the selection transistor and the memory transistor are formed as vertical MOS transistors. For this purpose a vertical sequence of suitably doped zones (2, 3, 4) in which trenches (5, 6) are produced and which are provided with gate dielectric (7, 8) and gate electrode (9, 10) is produced, in particular, by LPCVD epitaxy or by molecular-beam epitaxy.

Claims

1. A method of producing an arrangement containing self-amplifying dynamic MOS transistor memory cells, comprising the steps of;

providing a silicon substrate with a vertical sequence of doped zones which comprises at least a first doped zone a second doped zone disposed thereon and a third doped zone disposed thereon for a source zone, a channel zone and a drain zone of vertical MOS transistors,

etching a first trench and a second trench down into the first zone and which traverse the second zone and the third zone,

providing a surface of the first trench with a first gate dielectric and a surface of the second trench with a second gate dielectric,

forming a first gate electrode in the first trench and forming a second gate electrode in the second trench,

producing a third trench which cuts through the first doped zone, the second doped zone and the third doped zone between the first trench and the second trench,

providing the third trench with a first isolation structure at least in a region of the first doped zone and of the second doped zone,

electrically interconnecting parts of the third doped zone that are separated by the third trench by an interconnect structure, and

producing a diode structure whose one terminal is connected in an electrically conducting manner to the third doped zone and whose other terminal is connected in an electrically conducting manner to that of the second gate electrode.

2. A method according to claim 1, further comprising the steps of:

doping the silicon substrate with a first conductivity type,

said first doped zone being provided by epitaxially growing a silicon layer doped with a second conductivity type opposite to the first conductivity type on the silicon substrate,

said second doped zone being provided by applying a silicon layer doped with the first conductivity type by one of low-pressure chemical vapour deposition epitaxy and molecular-beam epitaxy, and

said third doped zone being provided by applying a silicon layer doped with the second conductivity type by one of LPCVD epitaxy and molecular-beam epitaxy.

3. A method according to claim 1, wherein the diode structure is formed as a Schottky diode.

4. A method according to claim 1, wherein the diode structure is formed as an n⁺ -p diode.

5. A method according to claim 4, wherein

the second gate electrode is formed from doped polysilicon,

a doped polysilicon structure is produced which, with the second gate electrode, is the diode structure, and

the doped polysilicon structure is connected in an electrically conducting manner to the third doped zone.

6. A method according to claim 5, wherein

the second gate electrode is produced in the second trench in a height essentially corresponding to the level of the second doped zone,

the doped polysilicon structure is produced in the second trench above the second gate electrode,

a surface of the doped polysilicon structure is provided with a metal silicide layer,

a doped polysilicon strip is produced in which the metal silicide layer and the third doped zone overlap at least partly in each case.

7. A method according to claim 5, further comprising the step of,

producing a diffusion-barrier layer between the second gate electrode and the doped polysilicon structure.

8. A method according to one of claims 1, wherein

a dopant concentration in the first doped zone and in the third doped zone is in the range greater than or equal to 10¹⁹ cm^-3,

a dopant concentration in the second doped zone is in the range less than or equal to 10¹⁸ cm^-3,

the first gate dielectric and the second gate dielectric are formed by thermal oxidation at 700°

to 800°

C.

9. A method according to claim 1, wherein the interconnect structure is formed by the third trench composed of doped polysilicon of the same conductivity type as the third doped zone.

10. A method according to claim 1, further comprising the steps of:

forming a multiplicity of memory cells disposed in matrix fashion in the silicon substrate,

the first trench, the second trench and the third trench are each formed as parallel strips,

producing inside the first trench, a fourth trench which cuts through the first doped zone and in which a second isolation structure is formed which isolates at least parts of the first doped zone on either side of the fourth trench from one another,

producing inside the second trench, a fifth trench which cuts through the first doped zone and in which a third isolation structure is formed which isolates parts of the first doped zone, the second gate electrode and the diode structure on either side of the fifth trench from one another,

producing sixth trenches which cross the first trenches, the second trenches and third trenches, which extend down into the first doped zone without cutting through the first doped zone and which are filled with fourth isolation structures,

producing word lines which extend parallel to the sixth trenches and which are connected in an electrically conducting manner to the first gate electrodes via word-line contacts,

adjacent ones of said multiplicity of memory cells being arranged in a mirror-symmetrical manner along a word line,

connecting a part of the first doped zone that is disposed between the first trench and the third trench as a bit line and that part of the first doped zone that is disposed between the third trench and the second trench as supply-voltage line.