High-voltage lateral MOSFET SOI device having a semiconductor linkup region

• US 5,710,451 A
• Filed: 04/10/1996
• Issued: 01/20/1998
• Est. Priority Date: 04/10/1996
• Status: Expired due to Fees

• Current Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Merchant, Steven L.
• Primary Examiner(s): Levy, Stuart S.
• Assistant Examiner(s): Giordana, Adriana
• Application Number:
  US08/629,819
• Time in Patent Office: 650 Days
• Field of Search: 257/347, 257/141, 257/140, 257/409, 257/143, 257/145, 257/168, 257/349, 437/41, 437/40, 437/6
• US Class Current: 257/347
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 29/78645 with multiple gate

Abstract

A Semiconductor-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate, and a lateral MOSFET on the buried insulating layer. The MOSFET includes a semiconductor surface layer on the buried insulating layer and has a source region of a first conductivity type, a channel region of a second conductivity type opposite to that of the first, an insulated gate electrode over the channel region and insulated therefrom, a lateral drift region of the second conductivity type, and a drain region of the first conductivity type laterally spaced apart from the channel region by the drift region. A semiconductor linkup region of the first conductivity type is provided between the channel region and the drift region and extends substantially through the semiconductor surface layer, and the source region of the device is electrically coupled to the drift region. This device configuration is particularly useful in providing a high-voltage p-channel MOS transistor using thin SOI high-voltage technology normally associated with fabricating n-channel devices.

Claims

1. A Semiconductor-On-Insulator (SOI) device comprising a semiconductor substrate, a buried insulating layer on said substrate, and a lateral MOSFET on said buried insulating layer, said MOSFET comprising a semiconductor surface layer on said buried insulating layer and having a source region of a first conductivity type, a channel region of a second conductivity type opposite to that of the first, an insulated gate electrode over said channel region and insulated therefrom, a lateral drift region of said second conductivity type, and a drain region of said first conductivity type and laterally spaced apart from said channel region by said drift region, characterized in that a semiconductor linkup region of said first conductivity type is provided between said channel region and said drift region and extends substantially through said semiconductor surface layer, and in that said source region is electrically coupled to said drift region.

2. An SOI device as in claim 1, wherein said first conductivity type is p type and said second conductivity type is n type.

3. An SOI device as in claim 1, wherein said first conductivity type is n type and said second conductivity type is p type.

4. An SOI device as in claim 1, wherein said linkup region extends from an upper surface of said semiconductor surface layer down to said buried insulating layer.

5. An SOI device as in claim 1, characterized in that at least a part of said lateral drift region between said linkup region and said drain region is thinner than a remaining part of said semiconductor surface layer.

6. An SOI device as in claim 1, characterized in that a surface insulating layer is provided on said drift region, and in that a conductive field plate is provided on said surface insulating layer and over at least a part of said drift region, said conductive field plate being electrically coupled to said drain region.

7. An SOI device as in claim 1, characterized in that a buffer region of said second conductivity type and having a higher doping concentration than that of said drift region is provided between said linkup region and said drift region.

8. An SOI device as in claim 1, characterized in that said linkup region comprises a surface region of said first conductivity type and having a higher doping concentration than that of a remaining part of said linkup region.