Lateral MOSFET with modified field plates and damage areas

• US 5,710,455 A
• Filed: 07/29/1996
• Issued: 01/20/1998
• Est. Priority Date: 07/29/1996
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Weitzel, Charles E., Bhatnagar, Mohit, Zunino, Michael
• Primary Examiner(s): Whitehead, Jr., Carl W.
• Application Number:
  US08/681,683
• Time in Patent Office: 540 Days
• Field of Search: 257/491, 257/492, 257/493, 257/213, 257/291, 257/292, 257/293, 257/294, 257/401, 257/402, 257/404, 257/487, 257/488
• US Class Current: 257/472
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A FET including a channel region and a drift region in a channel layer with a source in the channel region and a drain in the drift region. The current channel between the source and drain defining a straight transistor portion and a curved transistor portion. An oxide with a thin portion overlying the channel region and a thick portion overlying the drift region, and a gate on the thin oxide overlying the current channel. A drain field plate and a gate field plate on the thick oxide with spaced apart edges and a damaged region underlying the edges of the field plates only in the curved transistor portion to reduce electric fields at the edges of the field plates. Also, the current channel has a greater length and the edges are spaced apart farther in the curved transistor portions.

Claims

1. A field effect transistor comprising:

a substrate including an area with a first conductivity type;

a channel layer positioned on the substrate and defining a surface, the channel layer having a second conductivity type and a first doping concentration;

a laterally extending drift region defined in the channel layer, the drift region having the second conductivity type and a second doping concentration higher than the first doping concentration;

a first current carrying terminal positioned in electrical contact with the channel layer, the first current carrying terminal including a first contact region having the second conductivity type and a third doping concentration greater than the second doping concentration, the first contact region being defined in the channel layer adjacent the surface thereof and spaced from the drift region so as to define a channel region in the channel layer, the first current carrying terminal further including a first ohmic metal contact on the surface of the channel layer and in electrical contact with the first contact region;

a second current carrying terminal positioned in electrical contact with the drift region, the second current carrying terminal including a second contact region having the second conductivity type and the third doping concentration, the second contact region being defined in the channel layer adjacent the surface thereof and adjacent the drift region, the second current carrying terminal further including a second ohmic metal contact on the surface of the channel layer and in electrical contact with the second contact region;

the drift region, the first contact region, the channel region and the second contact region extending laterally, generally parallel with the surface of the channel layer and defining a straight transistor portion and a curved transistor portion;

a dielectric layer positioned on the channel layer and including a first portion with a first thickness overlying the channel region and a second portion with a second thickness greater than the first thickness overlying the drift region, the second portion extending laterally from the first portion to adjacent the second metal ohmic contact;

a control terminal including a third metal contact positioned on a surface of the first portion of the dielectric layer overlying the channel region;

the second ohmic metal contact having a first field plate electrically attached to the second metal contact and positioned on the second portion of the dielectric layer so as to define an edge extending toward the control terminal; and

a damaged region defined in the drift region and underlying the edges of the first field plate and the third metal contact only in the curved transistor portion to reduce electric fields at the edges of the first field plate and the third metal contact.

2. A field effect transistor as claimed in claim 1 wherein the substrate and channel layer are formed from a silicon carbide material system.

3. A field effect transistor as claimed in claim 1 wherein the substrate includes a subchannel layer defining the area with the first conductivity type, the subchannel layer and the channel layers being epitaxial layers.

4. A field effect transistor as claimed in claim 1 wherein the edge of the first field plate extends toward the control terminal a first distance in the straight transistor portion and a second distance, greater than the first distance, in the curved transistor portion.

5. A field effect transistor as claimed in claim 1 wherein the third metal contact includes a second field plate electrically attached to the third metal contact and positioned on the second portion of the dielectric layer so as to define an edge extending toward the second current carrying terminal, the edge of the second field plate being spaced from the edge of the first field plate.

6. A field effect transistor as claimed in claim 5 wherein the edge of the second field plate is spaced from the edge of the first field plate a first distance in the straight transistor portion and a second distance, greater than the first distance, in the curved transistor portion.

7. A field effect transistor as claimed in claim 1 wherein the first contact region of the first current carrying terminal and the second contact region of the second current carrying terminal define a current channel therebetween, and the current channel has a first length in the straight transistor portion and a second length, greater than the first length, in the curved transistor portion.

8. A field effect transistor comprising:

a substrate formed from a silicon carbide material system and including a first conductivity type area;

a channel layer positioned on the first conductivity type area of the substrate and defining a surface, the channel layer having a second conductivity type and a first doping concentration;

a laterally extending drift region defined in the channel layer, the drift region having the second conductivity type and a second doping concentration higher than the first doping concentration;

a source terminal positioned in electrical contact with the channel layer, the source terminal including a source contact region having the second conductivity type and a third doping concentration greater than the second doping concentration, the source contact region being defined in the channel layer adjacent the surface thereof and spaced from the drift region so as to define a channel region in the channel layer, the source terminal further including a source contact on the surface of the channel layer and in electrical contact with the source contact region;

a drain terminal positioned in electrical contact with the drift region, the drain terminal including a drain contact region having the second conductivity type and the third doping concentration, the drain contact region being defined in the channel layer adjacent the surface thereof and adjacent the drift region, the drain terminal further including a drain contact on the surface of the channel layer and in electrical contact with the drain contact region, the source contact region and the drain contact region defining a current channel therebetween including the channel region and a portion of the drift region;

the current channel extending laterally, generally parallel with the surface of the channel layer and defining a straight transistor portion and a curved transistor portion, and the current channel having a first length in the straight transistor portion and a second length, greater than the first length, in the curved transistor portion;

an oxide layer positioned on the channel layer and including a first portion with a first thickness overlying the channel region and a second portion with a second thickness greater than the first thickness overlying the drift region, the second portion extending laterally from the first portion to adjacent the drain contact;

a gate terminal including a gate contact positioned on a surface of the first portion of the oxide layer overlying a portion of the channel region in the current channel;

the drain contact having a first field plate electrically attached to the drain contact and positioned on the second portion of the oxide layer so as to define an edge extending toward the gate terminal; and

a damaged region defined in the drift region and underlying the edges of the first field plate and the gate contact in the curved transistor portion to reduce electric fields at the edges of the first field plate and the gate contact.

9. A field effect transistor as claimed in claim 8 wherein the edge of the first field plate extends toward the gate terminal a first distance in the straight transistor portion and a second distance, greater than the first distance, in the curved transistor portion.

10. A field effect transistor as claimed in claim 8 wherein the gate contact has a second field plate electrically attached to the gate contact and positioned on the second portion of the oxide layer so as to define an edge extending toward the drain terminal.

11. A field effect transistor as claimed in claim 10 wherein the edge of the second field plate is spaced from the edge of the first field plate a first distance in the straight transistor portion and the edge of the second field plate is spaced from the edge of the first field plate a second distance, greater than the first distance, in the curved transistor portion.

12. A field effect transistor comprising:

a substrate formed from a silicon carbide material system and including a first conductivity type area;

a channel layer positioned on the first conductivity type area of the substrate and defining a surface, the channel layer having a second conductivity type and a first doping concentration;

a laterally extending drift region defined in the channel layer, the drift region having the second conductivity type and a second doping concentration higher than the first doping concentration;

a source terminal positioned in electrical contact with the channel layer, the source terminal including a source contact region having the second conductivity type and a third doping concentration greater than the second doping concentration, the source contact region being defined in the channel layer adjacent the surface thereof and spaced from the drift region so as to define a channel region in the channel layer, the source terminal further including a source contact on the surface of the channel layer and in electrical contact with the source contact region;

a drain terminal positioned in electrical contact with the drift region, the drain terminal including a drain contact region having the second conductivity type and the third doping concentration, the drain contact region being defined in the channel layer adjacent the surface thereof and adjacent the drift region, the drain terminal further including a drain contact on the surface of the channel layer and in electrical contact with the drain contact region, the source contact region and the drain contact region defining a current channel therebetween including the channel region and a portion of the drift region;

the current channel extending laterally, generally parallel with the surface of the channel layer and defining a straight transistor portion and a curved transistor portion, and the current channel having a first length in the straight transistor portion and a second length, greater than the first length, in the curved transistor portion;

an oxide layer positioned on the channel layer and including a first portion with a first thickness overlying the channel region and a second portion with a second thickness greater than the first thickness overlying the drift region, the second portion extending laterally from the first portion to adjacent the drain contact;

a gate terminal including a gate contact positioned on a surface of the first portion of the oxide layer overlying a portion of the channel region in the current channel;

the drain contact having a first field plate electrically attached to the drain contact and positioned on the second portion of the oxide layer so as to define an edge extending toward the gate terminal;

the gate contact having a second field plate electrically attached to the gate contact and positioned on the second portion of the oxide layer so as to define an edge extending toward the drain terminal, and the edge of the second field plate being spaced from the edge of the first field plate a first distance in the straight transistor portion and a second distance, greater than the first distance, in the curved transistor portion; and

a damaged region defined in the drift region and underlying the edges of the first and second field plates.

13. A field effect transistor comprising:

a substrate formed from a silicon carbide material system and including a first conductivity type area;

a channel layer positioned on the first conductivity type area of the substrate and defining a surface, the channel layer having a second conductivity type and a first doping concentration;

a laterally extending drift region defined in the channel layer, the drift region having the second conductivity type and a second doping concentration higher than the first doping concentration;

a source terminal positioned in electrical contact with the channel layer, the source terminal including a source contact region having the second conductivity type and a third doping concentration greater than the second doping concentration, the source contact region being defined in the channel layer adjacent the surface thereof and spaced from the drift region so as to define a channel region in the channel layer, the source terminal further including a source contact on the surface of the channel layer and in electrical contact with the source contact region;

a drain terminal positioned in electrical contact with the drift region, the drain terminal including a drain contact region having the second conductivity type and the third doping concentration, the drain contact region being defined in the channel layer adjacent the surface thereof and adjacent the drift region, the drain terminal further including a drain contact on the surface of the channel layer and in electrical contact with the drain contact region, the source contact region and the drain contact region defining a current channel therebetween including the channel region and a portion of the drift region;

the current channel extending laterally, generally parallel with the surface of the channel layer and defining a straight transistor portion and a curved transistor portion, and the current channel having a first length in the straight transistor portion and a second length, greater than the first length, in the curved transistor portion;

an oxide layer positioned on the channel layer and including a first portion with a first thickness overlying the channel region and a second portion with a second thickness greater than the first thickness overlying the drift region, the second portion extending laterally from the first portion to adjacent the drain contact;

a gate terminal including a gate contact positioned on a surface of the first portion of the oxide layer overlying a portion of the channel region in the current channel;

the drain contact having a first field plate electrically attached to the drain contact and positioned on the second portion of the oxide layer so as to define an edge extending toward the gate terminal;

the gate contact having a second field plate electrically attached to the gate contact and positioned on the second portion of the oxide layer so as to define an edge extending toward the drain terminal, and the edge of the second field plate being spaced from the edge of the first field plate a first distance in the straight transistor portion and a second distance, greater than the first distance, in the curved transistor portion; and

a damaged region defined in the drift region and underlying the edges of the first and second field plates only in the curved transistor portion to reduce electric fields at the edges of the first field plate and the third metal contact.