EEPROM and method for fabricating the same
First Claim
1. An EEPROM, comprising:
- a gate oxide film and a floating gate stacked on a semiconductor substrate;
a first interlayer insulating film formed on all exposed surfaces of the floating gate and the semiconductor substrate;
a selecting gate overlapping with the first interlayer insulating film from an upper surface of the floating gate to a portion of the semiconductor substrate;
a drain electrode and a source electrode formed in the semiconductor substrate which overlap with a portion of the floating gate and a portion of the selecting gate, respectively;
a second interlayer insulating film formed on all exposed surfaces of the first interlayer insulating film and the selecting gate;
a contact hole formed in the second interlayer insulating film, exposing the selecting gate; and
a control gate which is in touch with the selecting gate through the contact hole and shields a surface portion of the floating gate which is not overlapped by the selecting gate.
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Accused Products
Abstract
An EEPROM including a selecting gate which overlaps with one side of a floating gate and a certain part of a source electrode and a control gate which overlaps with the other side of the floating gate and a certain part of a drain electrode, is improved in charge coupling ratio, showing an increase in program efficiency even at low outer voltages. Application of low outer voltages to the EEPROM brings about a decrease in both the breakdown voltage and the junction breakdown voltage of the gate oxide film of peripheral transistors, allowing a shallow junction and a thin gate oxide film process to be possible. A shallow junction can be effected by an ion-implanting process which results in formation of a source electrode and a drain electrode.
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Citations
4 Claims
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1. An EEPROM, comprising:
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a gate oxide film and a floating gate stacked on a semiconductor substrate; a first interlayer insulating film formed on all exposed surfaces of the floating gate and the semiconductor substrate; a selecting gate overlapping with the first interlayer insulating film from an upper surface of the floating gate to a portion of the semiconductor substrate; a drain electrode and a source electrode formed in the semiconductor substrate which overlap with a portion of the floating gate and a portion of the selecting gate, respectively; a second interlayer insulating film formed on all exposed surfaces of the first interlayer insulating film and the selecting gate; a contact hole formed in the second interlayer insulating film, exposing the selecting gate; and a control gate which is in touch with the selecting gate through the contact hole and shields a surface portion of the floating gate which is not overlapped by the selecting gate. - View Dependent Claims (2, 3, 4)
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Specification