EEPROM and method for fabricating the same

• US 5,710,735 A
• Filed: 12/12/1996
• Issued: 01/20/1998
• Est. Priority Date: 07/18/1994
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Choi, Soo Han, Shin, Ki Soo
• Primary Examiner(s): Yoo, Do Hyun
• Application Number:
  US08/764,245
• Time in Patent Office: 404 Days
• Field of Search: 365/185.26, 365/185.01, 257/316, 257/319, 257/320, 257/321
• US Class Current: 365/185.26
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An EEPROM including a selecting gate which overlaps with one side of a floating gate and a certain part of a source electrode and a control gate which overlaps with the other side of the floating gate and a certain part of a drain electrode, is improved in charge coupling ratio, showing an increase in program efficiency even at low outer voltages. Application of low outer voltages to the EEPROM brings about a decrease in both the breakdown voltage and the junction breakdown voltage of the gate oxide film of peripheral transistors, allowing a shallow junction and a thin gate oxide film process to be possible. A shallow junction can be effected by an ion-implanting process which results in formation of a source electrode and a drain electrode.

Claims

1. An EEPROM, comprising:

a gate oxide film and a floating gate stacked on a semiconductor substrate;

a first interlayer insulating film formed on all exposed surfaces of the floating gate and the semiconductor substrate;

a selecting gate overlapping with the first interlayer insulating film from an upper surface of the floating gate to a portion of the semiconductor substrate;

a drain electrode and a source electrode formed in the semiconductor substrate which overlap with a portion of the floating gate and a portion of the selecting gate, respectively;

a second interlayer insulating film formed on all exposed surfaces of the first interlayer insulating film and the selecting gate;

a contact hole formed in the second interlayer insulating film, exposing the selecting gate; and

a control gate which is in touch with the selecting gate through the contact hole and shields a surface portion of the floating gate which is not overlapped by the selecting gate.

2. An EEPROM in accordance with claim 1, wherein said floating gate is of island type overlapping with only an active region of the semiconductor substrate.

3. An EEPROM in accordance with claim 1, wherein said selecting gate and said control gate are formed extending in one direction.

4. An EEPROM in accordance with claim 1, wherein said first interlayer insulating film is structured to be either an oxide film monolayer or an oxide-nitride-oxide multilayer.