Advanced parallel array processor (APAP)

• US 5,710,935 A
• Filed: 06/06/1995
• Issued: 01/20/1998
• Est. Priority Date: 11/13/1990
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Retter, Eric Eugene, Schoonover, Nicholas Jerome, Kogge, Peter Michael, Wilkinson, Paul Amba, Dieffenderfer, James Warren, Richardson, Robert Reist, Collins, Clive Allan, Rolfe, David Bruce, Dapp, Michael Charles, Barker, Thomas Norman, Lesmeister, Donald Michael, Kuchinski, David Christopher, Miles, Richard Ernest, Smoral, Vincent John, Knowles, Billy Jack, Nier, Richard Edward, Grice, Donald George, Stupp, James Robert
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US08/466,462
• Time in Patent Office: 959 Days
• Field of Search: 395/800, 395/476
• US Class Current: 712/20
• CPC Class Codes: F02B 2075/027 four
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/17368 non hierarchical topologies
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 15/803 Three-dimensional arrays or hypercubes
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Claims

1. A multi-processor memory element comprising:

on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for external communication from the chip, said chip having a single broadcast and control interface for processor-memory elements on said chip, wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a pluralitv of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

2. A multi-processor memory element comprising:

on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for external communication from the chip, said chip having a single broadcast and control interface for processor-memory elements on said chip, wherein the chips are coupled in a network as a mesh, and wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

3. A multi-processor memory element comprising:

on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for external communication from the chip, wherein the chips are coupled in a network as a torus, and wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memorv element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

4. A multi-processor memory element comprising:

on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for communication, wherein the processor-memory elements on the chip can broadcast in one clock cycle to all processor-memory elements on the chip, and wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a pME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

5. A multi-processor memory element comprising:

on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for communication, wherein the processor-memory elements on the chip have a store and forward mode, and wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node. said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

6. A multi-processor memory element comprising:

on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for communication, wherein the processor-memory elements on the chip have a store and forward mode for passing message, means examining a broadcast message in a processor-memory element was to whether it is a store and forward item, and if it is, local DMA controls enter the message and store the message in memory to free up the processor-memory element for other execution, and wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

7. A multi-processor memory element comprising:

on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for communication, wherein the processor-memory elements on the chip have a store and forward mode for passing message, means examining a broadcast message in a processor-memory element was to whether it is a store and forward item, and if it is not directed to the particular processor-memory elements the message is switched to an internal output port of the processor-memory element, and wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

8. A multi-processor memory element comprising:

on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for communication, means for processing operands of 1 to N words with a length defined by an instruction which enables a processor-memory element to perform operations on a single word length which may be a multiple of the processor-memory element word length, wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

9. A processor memory element comprising:

on a chip one or more processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for external communication, each processor-memory element having an instruction set architecture which includes an instruction for a processor-memory element status switch to control dynamic switch of modes between MIMD and SIMD, wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

10. A computer system, comprising:

a plurality of processor-memory elements each having accessible memory, means for initiating the operation of the processor-memory elements in SIMD mode, an external controller having means for broadcasting code to said processor-memory elements upon initiation of the system, means for initiating a subsequent MIMD mode switch in said processor-memory elements by an external command causing the processor-memory elements which receive the command to begin execution in MIMD switched mode, wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.