Methods of formation of semiconductor composite gate dielectric having multiple incorporated atomic dopants

• US 5,712,208 A
• Filed: 05/25/1995
• Issued: 01/27/1998
• Est. Priority Date: 06/09/1994
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Tobin, Philip J., Tseng, Hsing-Huang, Witek, Keith E.
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US08/449,964
• Time in Patent Office: 978 Days
• Field of Search: 437/24, 437/46, 437/40, 437/41, 437/160, 437/162, 437/240, 437/241, 437/242
• US Class Current: 438/770
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: Y10S 438/923 Diffusion through a layer

Abstract

A semiconductor dielectric (10) is formed by providing a base layer (12) having a surface. A thin interface layer (13) is formed at the surface of the base layer (12). The thin interface layer has a substantial concentration of both nitrogen and fluorine. A thermal oxide layer (14) is formed overlying the interface layer (13). A deposited dielectric layer (16) is formed overlying the thermal oxide layer (14). The deposited dielectric layer (16) is optionally densified by a thermal heat cycle. The deposited dielectric layer (16) has micropores that are misaligned to micropores in the thermal oxide layer (14) to provide enhanced features which the nitrogen/fluorine interface further improves the dielectric'"'"'s features.

Claims

1. A method for making a dielectric comprising the steps of:

providing a substrate having a surface portion;

oxidizing the surface portion of the substrate using a nitrogen-containing oxidant to form a nitrogen-containing dielectric, the nitrogen residing in a concentration most-heavily near the surface portion rather than at a top portion of the nitrogen-containing dielectric;

depositing a deposited dielectric layer over the nitrogen-containing dielectric, the deposited dielectric and the nitrogen-containing dielectric each containing micropores which misalign to one another;

forming a gate electrode overlying the deposited dielectric;

implanting fluorine into the gate electrode to form a fluorinated gate electrode; and

annealing the fluorinated gate electrode to drive the fluorine into the nitrogen-containing dielectric to form a fluorinated nitrogen-containing dielectric where the fluorine is also concentrated most heavily at the surface portion.

2. The method of claim 1, wherein the step of oxidizing the surface portion is performed with the nitrogen-containing gas being selected from a group consisting of:

nitrous oxide (N₂ O), nitric oxide (NO), nitrogen dioxide (NO₂), nitrogen (N₂) and ammonia (NH₃).

3. The method of claim 1, wherein the step of providing the substrate comprises providing a material selected from a group consisting of single-crystalline silicon and polycrystalline silicon.

4. The method of claim 1, wherein the step of implanting fluorine comprises implanting pure fluorine ions.

5. The method of claim 1, wherein the step of annealing the fluorinated gate electrode is performed at a temperature substantially in a range of 600°

to 1000°

C.

6. The method of claim 1, further comprising the step of introducing chlorine into the nitrogen-containing dielectric.

7. A method for making a dielectric comprising the steps of:

providing a substrate having a surface portion;

oxidizing the surface portion of the substrate to form an oxide layer having a first plurality of micropores;

annealing the oxide layer with a nitrogen-containing ambient to form a nitrogen-containing dielectric;

forming a deposited dielectric region overlying the nitrogen-containing dielectric wherein the deposited dielectric has a second plurality of micropores misaligned to the first plurality of micropores;

forming a gate electrode overlying the deposited dielectric;

implanting fluorine into the gate electrode to form a fluorinated gate electrode after the step of annealing the oxide layer; and

heating the fluorinated gate electrode to drive the fluorine into the nitrogen-containing dielectric to form a fluorinated nitrogen-containing dielectric.

8. The method of claim 7, wherein the step of annealing the oxide layer is performed in an ambient containing a gas selected from a group consisting of:

nitrous oxide (N₂ O), nitric oxide (NO), nitrogen dioxide (NO₂), and ammonia (NH₃).

9. The method of claim 7, wherein the step of providing the substrate comprises providing a material selected from a group consisting of single-crystalline silicon, polycrystalline silicon, interpolysilicon dielectric, and tunnel dielectric.

10. The method of claim 7, wherein the step of implanting fluorine comprises implanting pure fluorine ions.

11. The method of claim 7, wherein the step of annealing the fluorinated gate electrode is performed at a temperature substantially in a range of 600°

to 1000°

C.

12. The method of claim 7, further comprising the step of introducing chlorine into the nitrogen-containing dielectric.

13. A method for making a dielectric comprising the steps of:

providing a silicon substrate having a surface portion;

forming a nitrogen-containing thermal dielectric on the surface portion of the silicon substrate by exposing the silicon substrate to an oxygen containing thermal oxide growth species;

depositing a deposited oxide over the nitrogen-containing thermal dielectric;

forming a gate electrode overlying the deposited oxide; and

forming a fluorinated dielectric, which contains fluorine atoms, overlying the gate electrode,

wherein the fluorine atoms in the fluorinated dielectric are driven via heat through the gate electrode into the nitrogen-containing dielectric to form a fluorinated nitrogen-containing thermal dielectric from the nitrogen-containing thermal dielectric.

14. The method of claim 13, wherein the step of growing the fluorinated dielectric is performed by oxidizing a top surface portion of the gate electrode with O₂ and a fluorine-containing ambient, to form a fluorinated oxide.

15. The method of claim 13, further comprising the step of annealing the fluorinated oxide in a temperature range of 600°

to 1000°

C. to drive the fluorine into the nitrogen-containing dielectric to form the fluorinated nitrogen-containing dielectric.

16. The method of claim 14, wherein the step of forming the fluorinated dielectric comprises the steps of:

oxidizing a top surface of the gate electrode with O₂ to form an oxide layer; and

annealing the oxide layer in a fluorine-containing ambient to introduce fluorine into the oxide layer and to drive the fluorine into the nitrogen-containing dielectric.

17. The method of claim 14, Wherein the step of growing the fluorinated dielectric comprises the steps of:

oxidizing a top surface of the gate electrode with O₂ to form an oxide layer; and

implanting fluorine ions into the oxide layer.

18. The method of claim 14, further comprising the step of annealing the fluorinated dielectric in a temperature range of 600°

to 1000°

C. to drive the fluorine into the nitrogen-containing dielectric to form the fluorinated nitrogen-containing dielectric.

19. The method of claim 14, further comprising the step of introducing a chlorine-containing species into the surface portion of the silicon substrate during the step of forming the nitrogen-containing dielectric.