Semiconductor device including active matrix circuit

• US 5,712,495 A
• Filed: 03/10/1997
• Issued: 01/27/1998
• Est. Priority Date: 06/13/1994
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Suzawa, Hideomi
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/807,001
• Time in Patent Office: 323 Days
• Field of Search: 257/58, 257/59, 257/61, 257/72, 257/348, 257/350, 257/351, 257/353, 257/354, 257/408, 257/900
• US Class Current: 257/49
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A combination of a doping process and the use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.

Claims

1. A semiconductor device comprising:

a substrate having an insulating surface;

an active matrix circuit, having at least one first thin film transistor, formed on the insulating surface; and

a peripheral circuit, having at least one second thin film transistor, formed on the insulating surface, for driving the active matrix circuit,

wherein each of the first and second thin film transistors comprises

source and drain regions,

a channel region provided between the source and drain regions,

a gate electrode formed over the active region,

an insulating film comprising an oxide of the gate electrode formed on at least side surfaces thereof, and

side insulators formed adjacent to only sides of the gate electrode with said insulating film interposed therebetween, and

wherein the first thin film transistor further comprises offset regions formed below said side insulators without doped impurities between the source region and the channel region and between the channel region and the drain region, said offset region comprising the same material as and having the same conductivity as said channel region, and

the second thin film transistor further comprises lightly doped regions formed between the source region and the channel region and between the channel region and the drain region.

2. The device of claim 1 wherein a concentration of an impurity included in the source and drain regions of the first thin film transistor is lower than that of an impurity included in the source and drain of the second thin film transistor.

3. The device of claim 1 wherein the peripheral circuit includes a source driver and a gate driver.

4. The device of claim 1 wherein the semiconductor device further comprises a liquid crystal cell, and the first thin film transistor is a switching element for the liquid crystal cell.

5. A semiconductor device comprising:

a substrate having an insulating surface; and

a plurality of thin film transistors formed on the insulating surface,

wherein each of the thin film transistors comprises

a source and a drain regions,

a channel region provided between the source and the drain regions,

a gate electrode formed over the channel region,

an insulating film comprising an oxide of the gate electrode formed on at least side surfaces thereof, and

side insulators formed adjacent to only sides of the gate electrode with the insulating film interposed therebetween,

wherein at least one of the thin film transistors is provided as an active matrix circuit and at least another one of the thin film transistors is provided as a peripheral circuit for driving the active matrix circuit, and

wherein the one of the thin film transistors further comprises offset regions formed below the side insulators between the source region and the channel region and between the channel region and the drain region, said offset region comprising the same material as and the same conductivity as the channel region, and

the another one thin film transistor further comprises lightly doped regions formed between the source region and the channel region and between the channel region and the drain region.

6. The device of claim 5 wherein a concentration of an impurity included in the source and drain regions of the one thin film transistor is lower than that of an impurity included in the source and drain regions of the another one thin film transistor.

7. The device of claim 5 wherein the peripheral circuit includes a source driver and a gate driver.

8. The device of claim 5 wherein the semiconductor device further comprises a liquid crystal cell, and the one thin film transistor provided as the active matrix circuit is a switching element for the liquid crystal cell.

9. An active matrix type liquid crystal display device comprising:

a substrate having an insulating surface;

a pixel circuit, having at least one first thin film transistor, formed on the insulating surface;

a liquid crystal cell connected with the pixel circuit; and

a peripheral circuit, having at least one second thin film transistor, formed on the insulating surface, for driving the pixel circuit,

wherein each of the first and second thin film transistors comprises

source and drain regions, a channel region provided between the source and drain regions,

a gate electrode formed over the channel region,

an insulating film comprising an oxide of the gate electrode formed on at least side surfaces thereof, and

side insulators formed adjacent to only sides of the gate electrode with the insulating film interposed therebetween, and

wherein the first thin film transistor further comprises offset regions formed below said side insulators between the source region and the channel region and between the channel region and the drain region, said offset region comprising the same material as and having the same conductivity as the channel region, and

the second thin film transistor further comprises lightly doped regions formed between the source region and the channel region and between the channel region and the drain region.

10. The device of claim 9 wherein the pixel circuit has a plurality of pixels.

11. The device of claim 9 wherein the peripheral circuit includes a source driver and a gate driver.

12. An active matrix type liquid crystal display device comprising:

a substrate having an insulating surface;

a pixel circuit, having at least one first thin film transistor, formed on the insulating surface,

wherein the first thin film transistor comprises

first source and drain regions,

a first channel region provided between the first source and drain regions,

a first gate electrode formed over the first channel region,

a first insulating film comprising an oxide of the first gate electrode formed on at least side surfaces thereof, and

first side insulators formed adjacent to only sides of the gate electrode with the first insulating film interposed therebetween;

a liquid crystal cell connected with the pixel circuit; and

a peripheral circuit, having at least one second thin film transistor, formed on the insulating surface, for driving the pixel circuit,

wherein the second thin film transistor comprises

second source and drain regions,

a second channel region provided between the second source and drain regions,

a second gate electrode formed over the second channel region,

a second insulating film comprising an oxide of the second gate electrode formed on at least side surfaces thereof, and

second insulators formed adjacent to only sides of the second gate electrode with the second insulating film interposed therebetween,

wherein the first thin film transistor further comprises offset regions formed below the side insulators between the source region and the channel region and between the channel region and the drain region, said offset region comprising the same material as and having the same conductivity as the channel region, and

the second thin film transistor further comprises lightly doped regions formed between the source region and the channel region and between the channel region and the drain region, and

wherein a concentration of an impurity included in the first source and drain regions is lower than that of an impurity included in the second source and drain regions.

13. The device of claim 12 wherein the pixel circuit has a plurality of pixels.

14. The device of claim 12 wherein the peripheral circuit includes a source driver and a gate driver.