MOS Poly-Si thin film transistor with a flattened channel interface and method of producing same

• US 5,712,496 A
• Filed: 01/13/1993
• Issued: 01/27/1998
• Est. Priority Date: 01/17/1992
• Status: Expired due to Term

• Current Assignee: Seiko Instruments Incorporated (Seiko Group)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: Takahashi, Hiroshi, Kojima, Yoshikazu
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): GUAY, JOHN FRANCIS
• Application Number:
  US08/002,400
• Time in Patent Office: 1,840 Days
• Field of Search: 437/233, 257/64, 257/69, 257/67, 257/66, 257/347
• US Class Current: 257/64
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate

Abstract

A thin film field effect transistor has a three-layer structure including a polycrystalline semiconductor layer to be a channel region, a conductive layer to be a gate electrode and a insulating layer to be a gate insulating film between the channel region and the gate electrode. The roughness of an interface between the channel region and the gate insulating film is less than a few nm so that the current drivability of the transistor is improved.

Claims

1. A thin field effect transistor having a three-layer structure, comprising:

a polycrystalline semiconductor layer having a thickness of less than 0.3 μ

m and defining a channel region;

an insulating layer defining a gate insulating film contacting the polycrystalline semiconductor layer, so that the gate insulating film and the polycrystalline semiconductor layer contact one another at an interface; and

a conductive layer defining a gate electrode on the insulating layer so that the insulating layer is located between the channel and the gate electrode;

wherein the interface is substantially flat and has a surface roughness of less than 3 nm between the channel region and the gate insulating film, and the channel region has a number of grains more than 10.

2. A thin film field effect transistor as claimed in claim 1 wherein the flat interface has a surface roughness of less than 1/50 the thickness of the polycrystalline semiconductor layer.

3. A thin film field effect transistor device comprising a silicon substrate, a silicon oxide layer on said silicon substrate and a three-layer thin film field effect transistor structure on said silicon oxide layer, said three-layer structure comprising:

a polycrystalline semiconductor layer defining a channel region;

an insulating layer defining a gate insulating film contacting the polycrystalline semiconductor layer, so that the gate insulating film and the polycrystalline semiconductor layer contact one another at an interface; and

a conductive layer defining a gate electrode on the insulating layer so that the insulating layer is located between the channel region and the gate electrode;

wherein the interface is substantially flat at least between the channel region and the gate insulating film, wherein the silicon oxide layer and the polycrystalline semiconductor layer contact one another at a second interface which is substantially flat, and wherein the silicon oxide layer has, at the second interface, a surface roughness under a few nm.

4. A thin film field effect transistor device comprising a silicon substrate, a silicon oxide layer on said silicon substrate and a three-layer thin film field effect transistor structure on said silicon oxide layer, said three-layer structure comprising:

a polycrystalline semiconductor layer defining a channel region;

an insulating layer defining a gate insulating film contacting the polycrystalline semiconductor layer, so that the gate insulating film and the polycrystalline semiconductor layer contact one another at an interface; and

a conductive layer defining a gate electrode on the insulating layer so that the insulating layer is located between the channel region and the gate electrode;

wherein the interface is substantially flat at least between the channel region and the gate insulating film, wherein the silicon oxide layer and the polycrystalline semiconductor layer contact one another at a second interface which is substantially flat, wherein the silicon substrate and the silicon oxide layer contact one another at a third interface which is substantially flat, and wherein the silicon substrate has, at third interface, a surface roughness under a few nm.

5. A thin film field effect transistor device comprising a silicon substrate, a silicon oxide layer on said silicon substrate and a three-layer thin film field effect transistor structure on said silicon oxide layer, said three-layer structure comprising:

a polycrystalline semiconductor layer defining a channel region;

an insulating layer defining a gate insulating film contacting the polycrystalline semiconductor layer, so that the gate insulating film and the polycrystalline semiconductor layer contact one another at an interface; and

a conductive layer defining a gate electrode on the insulating layer so that the insulating layer is located between the channel region and the gate electrode;

wherein the interface is substantially flat at least between the channel region and the gate insulating film, and wherein the gate electrode contacts the silicon oxide layer and the gate insulating film contact the gate electrode to form a second interface which is substantially flat.

6. A thin film field effect transistor device as claimed in claim 5 wherein the gate electrode has, at the second interface, a surface roughness under 2 nm.