Linear phase detector for half-speed quadrature clocking architecture

• US 5,712,580 A
• Filed: 02/14/1996
• Issued: 01/27/1998
• Est. Priority Date: 02/14/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Baumgartner, Steven John, Paschal, Matthew James
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Wells, Kenneth B.
• Application Number:
  US08/599,997
• Time in Patent Office: 713 Days
• Field of Search: 327/2, 327/3, 327/7, 327/10, 327/12, 327/141, 327/144, 327/147, 327/148, 327/150, 327/159, 327/231, 327/237, 327/238, 327/254, 327/255, 375/371, 375/373, 375/375, 375/376, 375/359, 375/362, 375/364, 370/518, 370/544
• US Class Current: 327/12
• CPC Class Codes: H03D 13/001 in which a pulse counter is used followed by a conversion into an analog signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A linear phase detector used with half-speed quadrature clock architecture is provided. The linear phase detector includes a first circuit receiving a data signal, a first half-speed quadrature clock signal and a second half-speed quadrature clock signal. The first circuit generates an adjusted data signal and a polarity representing signal of the first half-speed quadrature clock signal. A high speed phase detector is coupled to the first circuit for generating a linear phase correction signal.

Claims

1. A linear phase detector used with half-speed quadrature clock architecture comprising:

a first circuit for receiving a data signal, a first half-speed quadrature clock signal, and a second half-speed quadrature clock signal;

said first circuit comprising;

means, responsive to said data signal, for generating an adjusted data signal;

means, responsive to said data signal and said second half-speed quadrature clock signal, for generating a polarity representing signal of said second half-speed quadrature clock signal; and

means, responsive to said polarity representing signal, for selecting an appropriate polarity of said first half-speed quadrature clock signal; and

a phase detector coupled to said first circuit for generating a linear phase correction.

2. The linear phase detector as recited in claim 1 wherein said means, responsive to said data signal, for generating said adjusted data signal comprises a flip-flop configured as a divide by two.

3. The linear phase detector as recited in claim 1 wherein said means, responsive to said data signal, for generating said adjusted data signal comprises an edge triggered D-type flip-flop configured to provide a rising edge on alternate rising edges of said data signal.

4. The linear phase detector as recited in claim 1 wherein said means, responsive to said data signal and said second half-speed quadrature clock signal, for generating said polarity representing signal of said second half-speed quadrature clock signal comprises a flip-flop for sampling said second half-speed quadrature clock signal with said data signal.

5. The linear phase detector as recited in claim 4 wherein said means, responsive to said polarity representing signal, for selecting said appropriate polarity of said first half-speed quadrature clock signal comprises an exclusive OR gate for XORing an output of said flip-flop with said first half-speed quadrature clock signal.

6. The linear phase detector as recited in claim 1 wherein said phase detector coupled to said first circuit for generating said linear phase correction signal comprises a pair of latches.

7. The linear phase detector as recited in claim 6 wherein said adjusted data signal is applied to a first one of said pair of latches for generating an UP correction signal.

8. The linear phase detector as recited in claim 7 wherein said appropriate polarity of said first half-speed quadrature clock signal is applied to a second one of said pair of latches for generating a DOWN correction signal.

9. A linear phase detector for use with half-speed quadrature clock architecture including a first half-speed quadrature clock signal and a second half-speed quadrature clock signal, the first and second half-speed quadrature clock signals being half-speed of a received data rate, said linear phase detector comprising:

a first circuit receiving the data signal, the first half-speed quadrature clock signal and the second half-speed quadrature clock signal;

said first circuit comprising;

first means, receiving the data signal, for generating an adjusted data signal;

second means, receiving the data signal and the second half-speed quadrature clock signal, for generating a polarity representing signal of the second half-speed quadrature clock signal; and

means, responsive to said polarity representing signal, for selecting an appropriate polarity of the first half-speed quadrature clock signal; and

a phase detector coupled to said first circuit for generating a linear phase correction signal.

10. The linear phase detector as recited in claim 9 wherein said first means for generating an adjusted data signal comprises a flip-flop configured as a divide by two.

11. The linear phase detector as recited in claim 9 wherein said second means for generating a polarity representing signal comprises a flip-flop configured for sampling the second half-speed quadrature clock signal with the data signal and wherein said means responsive to said polarity representing signal comprises an exclusive OR gate for XORing an output of said flip-flop with said first half-speed quadrature clock signal.

12. The linear phase detector as recited in claim 9 wherein said phase detector comprises a first latch receiving said generated adjusted data signal for generating an UP correction signal, and second latch receiving said appropriate polarity of said first half-speed quadrature clock signal for generating a DOWN correction signal, and wherein said generated UP correction signal is proportional to a phase difference between the data signal and the first half-speed quadrature clock signal and said generated DOWN correction signal is proportional to a width of the first half-speed quadrature clock signal.

13. The linear phase detector as recited in claim 9 comprising a demultiplexer to a demultiplex the data signal;

said demultiplexer comprising a pair of retiming latches clocked by the second half-speed quadrature clock signal.

14. A linear phase detector using a first half-speed quadrature clock signal and a second half-speed quadrature clock signal, said linear phase detector comprising:

a demultiplexer to demultiplex a data signal;

said demultiplexer comprising a pair of retiming latches docked by the second half-speed quadrature clock signal;

a first flip-flop receiving the data signal for generating a divided by two data signal;

a second flip-flop receiving the data signal and the second half-speed quadrature clock signal for generating a polarity representing signal of the second half-speed quadrature clock signal;

an exclusive OR gate for XORing an output of said second flip-flop and the first half-speed quadrature clock signal; and

a phase detector coupled to an output of said first flip-flop and said exclusive OR gate for generating a linear phase correction signal.

15. A linear phase detector for use with half-speed quadrature clock architecture comprising:

a first circuit for receiving a data signal, a first half-speed quadrature clock signal, and a second half-speed quadrature clock signal;

said first circuit comprising;

an adjusted data signal generator to generate an adjusted data signal responsive to the data signal;

a polarity signal generator receiving as inputs the data signal and the second half-speed quadrature clock signal to generate a polarity signal representative of the second half-speed quadrature clock signal;

a selector connected to the polarity signal generator and the first half-speed quadrature clock to select an appropriate polarity of the first half-speed quadrature clock signal; and

a phase detector coupled to the first circuit for generating a linear phase correction signal.

16. The linear phase detector of claim 15 wherein the linear phase correction signal comprises a first signal proportional to a phase difference between the data signal and the first half-speed quadrature clock signal, and a second signal proportional to a width of the first half-speed quadrature clock signal.