Full differential data qualification circuit for sensing a logic state

• US 5,712,581 A
• Filed: 12/21/1995
• Issued: 01/27/1998
• Est. Priority Date: 08/02/1993
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kaylor, Scott Alan
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): DRISCOLL, BENJAMIN
• Application Number:
  US08/576,270
• Time in Patent Office: 768 Days
• Field of Search: 307/354, 307/355, 307/359, 307/356, 307/475, 326/21, 326/35, 327/63, 327/65, 327/71, 327/74, 327/77, 327/67
• US Class Current: 327/74
• CPC Class Codes: H03K 3/02337 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165
• CPC Class Codes: H03K 5/088 modified by switching, e.g. by a periodic signal or by a signal in synchronism with the transitions of the output signal

Abstract

A data qualification circuit (11) comprises a comparator (28), a first threshold circuit (33), and a second threshold circuit (41). A differential input signal is applied to the data qualification circuit (11). A first threshold circuit (33) is enabled by a zero logic state at the output of comparator (28). The first threshold circuit (33) sets a one logic state threshold voltage which the differential input signal must overcome for the comparator (28) to generate a one logic state. A second threshold circuit (41) is enabled by a zero logic state at the output of comparator (28). The second threshold circuit (41) sets a zero logic state threshold voltage which the differential input signal must overcome for the comparator (28) to generate a zero logic state.

Claims

1. A data qualification circuit for translating an applied differential input voltage to an output signal having first or second predetermined level logic states, comprising:

a comparator having first and second inputs and at least one output at which the output signal is provided;

a first threshold circuit responsive to the output signal being at the second logic level state for providing a first threshold level signal across said first and second inputs of said comparator, said first threshold circuit being programmable to adjust a magnitude of said first threshold level signal;

a second threshold circuit responsive to the output signal being at the first logic level state for providing a second threshold level signal across said first and second inputs of said comparator, said second threshold circuit being programmable to adjust a magnitude of said second threshold level signal; and

an input circuit responsive to the differential input voltage for providing an output signal across said first and second inputs of said comparator, said first and second threshold level signals being summed with said output signal of said input circuit as said first and second threshold circuits are rendered operative in response to said output signal from said comparator.

2. A data qualification circuit as recited in claim 1 wherein said first and second threshold levels signals have different signal magnitudes.

3. A data qualification circuit as recited in claim 1 further including a load circuit for summing signals applied to said first and second inputs of said comparator, said load circuit including a first and a second terminal coupled respectively to said first and second inputs of said comparator.

4. A data qualification circuit as recited in claim 3 wherein said load circuit comprises:

a first resistor including a terminal coupled to a terminal of a power supply and a second terminal corresponding to said first terminal of said load circuit; and

a second resistor including a terminal coupled to said terminal of said power supply and a second terminal corresponding to said second terminal of said load circuit.

5. A data qualification circuit as recited in claim 3 wherein said input circuit comprises a voltage to current circuit responsive to the applied input differential voltage and providing a differential current to said load circuit.

6. A data qualification circuit as recited in claim 3 wherein said first threshold circuit comprises:

a voltage to current circuit responsive to an applied reference voltage and providing a differential current corresponding to said first reference voltage; and

a switch circuit responsive to the output signal being in the second logic state, said switch circuit coupling said voltage to current circuit to said load circuit.

7. A data qualification circuit as recited in claim 6 further including a digital to analog converter for providing said applied reference voltage, said digital to analog converter being programmable for changing said applied reference voltage.

8. A data qualification circuit as recited in claim 3 wherein said second threshold circuit comprises:

a voltage to current circuit responsive to an applied reference voltage and providing a differential current corresponding to said second reference voltage; and

a switch circuit responsive to the output signal being in the first logic state, said switch circuit coupling said voltage to current circuit to said load circuit.

9. A data qualification circuit as recited in claim 8 further including a digital to analog converter for providing said applied reference voltage, said digital to analog converter being programmable for changing said applied reference voltage.

10. A circuit for translating an applied differential input voltage to an output signal having first or second predetermined level logic states, comprising:

a comparator having first and second inputs and at least one output at which the output signal is provided;

a load circuit for summing signals applied thereto, said load circuit having a first terminal coupled to said first input of said comparator and a second terminal coupled to said second input of said comparator;

a first threshold circuit responsive to the output signal being at the second logic level state for providing a first threshold level signal across said first and second terminals of said load circuit, said first threshold circuit being programmable to adjust a magnitude of said first threshold level signal;

a second threshold circuit responsive to the output signal being at the first logic level state for providing a second threshold level signal across said first and second terminals of said load circuit, said second threshold circuit being programmable to adjust a magnitude of said second threshold level signal; and

an input circuit responsive to the differential input voltage for providing an output signal across said first and second terminals of said load circuit, said first and second threshold level signals being summed with said output signal of said input circuit as said first and second threshold circuits are rendered operative in response to said output signal from said comparator.

11. A circuit as recited in claim 10 wherein said load circuit comprises a first resistor including a first terminal coupled to a terminal of a power supply and a second terminal corresponding to said first terminal of said load circuit and a second resistor including a first terminal coupled to said terminal of said power supply and a second terminal corresponding to said second terminal of said load circuit, and wherein said input circuit, first threshold circuit, and second threshold circuit each provide a differential current signal corresponding respectively to said output signal of said input circuit, said first threshold level signal, and said second threshold level signal.

12. A circuit as recited in claim 11 wherein said input circuit comprises a voltage to current circuit responsive to said applied differential voltage and providing said differential current signal to said load circuit, said voltage to current circuit comprising:

a first transistor including a control terminal coupled to a first input, a first terminal coupled to said first terminal of said load circuit, and a second terminal;

a second transistor including a control terminal coupled to a second input, a first terminal coupled to said second terminal of said load circuit, and a second terminal, said first and second inputs receiving said differential input voltage;

a resistor coupled between said second terminal of said first transistor and said second terminal of said second transistor;

a first current source for biasing said first transistor including a terminal coupled to said second terminal of said first transistor; and

a second current source for biasing said second transistor including a terminal coupled to said second terminal of said second transistor.

13. A circuit for translating an applied differential input voltage to an output signal having first or second predetermined level logic states, comprising:

a comparator having first and second inputs and at least one output at which the output signal is provided;

a load circuit for summing signals applied thereto, said load circuit having a first terminal coupled to said first input of said comparator and a second terminal coupled to said second input of said comparator, said load circuit comprises a first resistor including a first terminal coupled to a terminal of a power supply and a second terminal corresponding to said first terminal of said load circuit and a second resistor including a first terminal coupled to said terminal of said power supply and a second terminal corresponding to said second terminal of said load circuit;

a first threshold circuit responsive to the output signal being at the second logic level state for providing a first threshold level signal across said first and second terminals of said load circuit, said first threshold circuit comprises a switch circuit responsive to the output signal being at the second logic level, said switch circuit including a first input, a second input, a first output coupled to said first terminal of said load circuit, and a second output coupled to said second terminal of said load circuit;

a voltage to current circuit responsive to an applied reference voltage and providing said differential current signal to said load circuit when coupled thereto by said switch circuit, said voltage to current circuit comprising;

a first transistor including a control terminal coupled to a first input of said first threshold circuit, a first terminal coupled to said first input of said switch circuit, and a second terminal;

a second transistor including a control terminal coupled to a second input of said first threshold circuit, a first terminal coupled to said second input of said switch circuit, and a second terminal, said first and second inputs of said first threshold circuit receiving said applied reference voltage;

a resistor coupled between said second terminal of said first transistor and said second terminal of said second transistor;

a first current source for biasing said first transistor including a terminal coupled to said second terminal of said first transistor;

a second current source for biasing said second transistor including a terminal coupled to said second terminal of said second transistor;

a second threshold circuit responsive to the output signal being at the first logic level state for providing a second threshold level signal across said first and second terminals of said load circuit; and

an input circuit responsive to the differential input voltage for providing an output signal across said first and second terminals of said load circuit, said first and second threshold level signals being summed with said output signal of said input circuit as said first and second threshold circuits are rendered operative in response to said output signal from said comparator;

wherein said input circuit, first threshold circuit, and second threshold circuit each provide a differential current signal corresponding respectively to said output signal of said input circuit, said first threshold level signal, and said second threshold level signal.

14. A circuit as recited in claim 13 wherein a digital to analog converter provides said applied reference voltage to said first and second inputs of said first threshold circuit.

15. A circuit as recited in claim 13 wherein said second threshold circuit comprises:

a switch circuit responsive to the output signal being at the first logic level, said switch circuit including a first input, a second input, a first output coupled to said second terminal of said load circuit, and a second output coupled to said first terminal of said load circuit;

a voltage to current circuit responsive to an applied reference voltage and providing said differential current signal to said load circuit when coupled thereto by said switch circuit, said voltage to current circuit comprising;

a first transistor including a control terminal coupled to a first input of said second threshold circuit, a first terminal coupled to said first input of said switch circuit, and a second terminal;

a second transistor including a control terminal coupled to a second input of said second threshold circuit, a first terminal coupled to said second input of said switch circuit, and a second terminal, said first and second inputs of said second threshold circuit receiving said applied reference voltage;

a resistor coupled between said second terminal of said first transistor and said second terminal of said second transistor;

a first current source for biasing said first transistor including a terminal coupled to said second terminal of said first transistor; and

a second current source for biasing said second transistor including a terminal coupled to said second terminal of said second transistor.

16. A circuit as recited in claim 15 wherein a digital to analog converter provides said applied reference voltage to said first and second inputs of said second threshold circuit.

17. A full differential data qualification circuit for translating an applied differential input voltage to an output signal having first or second predetermined logic level states, the full differential data qualification circuit comprising:

a comparator including a first input, a second input, and at least one output at which the output signal is provided;

a first threshold circuit for providing a first threshold level signal across said first and second inputs of said comparator, said first threshold circuit including a first input, a second input, a control input coupled to said output of said comparator, a first output coupled to said first input of said comparator, and a second output coupled to said second input of said comparator, said first and second inputs of said first threshold circuit being responsive to an applied first reference voltage, said first and second outputs providing said first threshold level signal when rendered operative by the output signal being in the second predetermined logic level state, said first threshold circuit being programmable to adjust a magnitude of said first threshold level signal;

a second threshold circuit for providing a second threshold level signal across said first and second inputs of said comparator, said second threshold circuit including a first input, a second input, a control input coupled to said output of said comparator, a first output coupled to said second input of said comparator, and a second output coupled to said first input of said comparator, said first and second inputs of said second threshold circuit being responsive to an applied second reference voltage,. said first and second outputs providing said second threshold level signal when rendered operative by the output signal being in the first predetermined logic level state, said second threshold circuit being programmable to adjust a magnitude of said second threshold level signal; and

an input circuit for providing an output signal across said first and second inputs of said comparator, said input circuit including a first input, a second input, a first output coupled to said first input of said comparator, and a second input coupled to said second input of said comparator, said first and second inputs receiving the applied differential input voltage.

18. A full data qualification circuit as recited in claim 17 wherein a first digital to analog converter provides said first reference voltage, wherein a second digital to analog converter provides said second reference voltage thereby allowing said first and second threshold signals to be of different magnitudes.

19. A full data qualification circuit as recited in claim 17 further including a load circuit for summing signals provided by said input circuit, said first threshold circuit, and said second threshold circuit, said load circuit comprising a first resistor including a first terminal coupled to a terminal of a power supply and a second terminal coupled to said first input of said comparator, and a second resistor including a first terminal coupled to said terminal of said power supply and a second terminal coupled to said second input of said comparator.

20. A full data qualification circuit as recited in claim 19 wherein the applied differential input voltage is converted to a differential current by said input circuit and either said first threshold circuit or second threshold circuit rendered operative by the output signal provides a differential current.