Image display scanning circuit with outputs from sequentially switched pulse signals

• US 5,712,653 A
• Filed: 12/23/1994
• Issued: 01/27/1998
• Est. Priority Date: 12/27/1993
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Sakai, Tamotsu, Kubota, Yasushi, Katoh, Kenichi, Yoneda, Hiroshi
• Primary Examiner(s): Powell, Mark R.
• Application Number:
  US08/363,217
• Time in Patent Office: 1,131 Days
• Field of Search: 345/94, 345/27, 345/100, 345/165, 345/168, 345/92, 326/95, 326/104, 326/105, 365/154, 341/109, 341/55
• US Class Current: 345/100
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

An active-matrix image display device which includes n shift registers, analog switches for sampling video input signals and a data-signal-line driving circuit to which n series of clock signals and n×m series of video input signals are input, and controls the analog switches according to the result of a logic operation of output pulses from successive l stages in the shift registers. A scanning circuit without using shift registers. Here, n is an integer not smaller than one, m and l are integers not smaller than two. With the image display device, sampling of video signals is surely executed without increasing the number of shift registers. It is thus possible to reduce the size and weight of the image display device and to decrease the defect rate thereof. Moreover, the scanning circuit achieves a higher yield compared with a conventional scanning circuit using a shift register.

Claims

1. A scanning circuit comprising:

m lines of pulse signal lines for use in inputting signals;

l lines of output signal lines for use in outputting signals; and

switching means for sequentially switching signals to be output to said output signal lines between ON and OFF according to signals input to said pulse signal lines,

wherein said switching means switches signals to be output to said output signal lines between ON and OFF by a logic operation based on n signals input to n input lines of said switching means, said n signals being taken from selected combinations of the m lines of said pulse signal lines, each combination of the n lines used in a logic operation produces an output signal on a different one of said output signals lines, n satisfying a condition of mCn≧

l where n, m and l are positive integers, and wherein a plurality of output signal lines are not turned ON simultaneously.

2. The scanning circuit according to claim 1,

wherein signals are inputted to said pulse signal lines so that (1) one of said pulse signal lines is reset and (2) another next sequentially operated pulse signal line is set after a predetermined time has elapsed since the reset of said one of said pulse signal lines.

3. The scanning circuit according to claim 1,

wherein signals to be input to said pulse signal lines are set so that said pulse signal lines in a set state go into a reset state for a predetermined time immediately before a combination of said pulse signals in the set state changes.

4. The scanning circuit according to claim 1,

wherein threshold voltages of said switching means are adjusted so that said output signal lines are set or reset only when a result of the logic operation is true and is kept true for a predetermined time.

5. The scanning circuit according to claim 2,

wherein said switching means is arranged so that said output signal lines are set or reset only when a result of the logic operation is true and is kept true for a predetermined time.

6. The scanning circuit according to claim 3,

wherein said switching means is arranged so that said output signal lines are set or reset only when a result of the logic operation is true and is kept true for a predetermined time.

7. The scanning circuit according to claim 1, further comprising an encoder for outputting signals to said pulse signal lines according to start pulses and clock pulses.

8. The scanning circuit according to claim 2, further comprising an encoder for outputting signals to said pulse signal lines according to start pulses and clock pulses.

9. The scanning circuit according to claim 3, further comprising an encoder for outputting signals to said pulse signal lines according to start pulses and clock pulses.

10. A scanning circuit as in claim 1 wherein n is an integer from 2 to 4.