Voltage multiplying DC-DC converter for a thin film transistor liquid crystal display
First Claim
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1. A DC-DC converter for a TFT-LCD, comprising:
- a first PMOS type transistor and a first NMOS type transistor which have source terminals connected to a power signal line and a ground line, respectively, gate terminals connected in common to a first polar signal line, and drain terminals;
a second PMOS type transistor and a second NMOS type transistor which have source terminals connected to the power signal line and the ground line, respectively, gate terminals connected in common to a second polar signal line, and drain terminals;
first and second diodes which have anode terminals connected to the power signal line, respectively, and cathode terminals;
third and fourth diodes which have anode terminals connected to the cathode terminals of the first and second diodes, respectively, and cathode terminals;
a first capacitor which is connected between the cathode terminal of the first diode and the drain terminal of the first PMOS type transistor connected in common to the drain terminal of the first NMOS type transistor;
a second capacitor which is connected between the cathode terminal of the second diode and the drain terminal of the second PMOS type transistor connected in common to the drain terminal of the second NMOS type transistor; and
a third capacitor which is connected between the ground line and the cathode terminal of the third diode connected in common to the cathode terminal of the fourth diode.
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Abstract
A DC-DC converter for a TFT-LCD includes first and second switches which are turned on/off in opposition according to a polar signal and third and fourth switches which are turned on/off in opposition according to an inverse polar signal. First and second diodes form electric paths in accordance with the first and the second switches, and third and fourth diodes form electric paths in accordance with the third and fourth switches. A first capacitor is charged when the electric paths of the first and second diodes are provided and a second capacitor is charged when the electric paths of the third and fourth diodes are provided. A third capacitor is charged by the electric charges of the first and the second capacitors. Using this circuit, a DC-DC power converter can be constructed which uses very little power and therefore can be employed in a TFT-LCD of portable information processing equipment.
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Citations
3 Claims
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1. A DC-DC converter for a TFT-LCD, comprising:
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a first PMOS type transistor and a first NMOS type transistor which have source terminals connected to a power signal line and a ground line, respectively, gate terminals connected in common to a first polar signal line, and drain terminals; a second PMOS type transistor and a second NMOS type transistor which have source terminals connected to the power signal line and the ground line, respectively, gate terminals connected in common to a second polar signal line, and drain terminals; first and second diodes which have anode terminals connected to the power signal line, respectively, and cathode terminals; third and fourth diodes which have anode terminals connected to the cathode terminals of the first and second diodes, respectively, and cathode terminals; a first capacitor which is connected between the cathode terminal of the first diode and the drain terminal of the first PMOS type transistor connected in common to the drain terminal of the first NMOS type transistor; a second capacitor which is connected between the cathode terminal of the second diode and the drain terminal of the second PMOS type transistor connected in common to the drain terminal of the second NMOS type transistor; and a third capacitor which is connected between the ground line and the cathode terminal of the third diode connected in common to the cathode terminal of the fourth diode. - View Dependent Claims (2)
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3. A DC-DC converter for a TFT-LCD, comprising:
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a switch circuit which inputs a polar signal and an inverse polar signal and outputs a first pulsed voltage to a first node and a second pulsed voltage to a second node; a charge circuit connected between the first and second nodes and an output node, the charge circuit further connected to a power source having a power source voltage such that third and fourth nodes within the charging circuit are intermittently raised by a capacitor to a charging voltage level which exceeds the power source voltage;
the third and fourth nodes each connected through a diode to the output node; anda smoothing capacitor connected to the output node.
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Specification
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Current AssigneeSamsung Display Company Limited (Samsung Electronics Co. Ltd.)
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Original AssigneeSamsung Electronics Co. Ltd.
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InventorsMoon, Seung-hwan
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Primary Examiner(s)Sterrett, Jeffrey L.
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Application NumberUS08/633,288Time in Patent Office651 DaysField of Search363/59, 363/60US Class Current363/60CPC Class CodesG09G 3/2011 by amplitude modulationG09G 3/3696 Generation of voltages supp...
