Flexible dram array

• US 5,712,823 A
• Filed: 02/02/1996
• Issued: 01/27/1998
• Est. Priority Date: 12/14/1994
• Status: Expired due to Term

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Gillingham, Peter B.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/597,510
• Time in Patent Office: 725 Days
• Field of Search: 365/230.06, 365/230.08, 365/238.5, 365/203, 365/189.01, 365/189.11, 365/185.33, 365/185.23, 365/185.28
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A DRAM array comprised of plural wordlines and plural bitlines, bit charge storage capacitors associated with the bitlines and wordlines, cell access field effect transistors (FETs) having their gates connected to the wordlines and their source-drain circuits connected between the bitlines and the charge storage cells, for enabling reading or writing data from or to the charge storage capacitors, and programmable addressing apparatus for causing the wordlines, once addressed, to selectively enable either one or more than one cell access FET, whereby data can be selectively read from or written to one or more than one charge storage capacitor.

Claims

1. A method of storing data in a DRAM array comprised of cells coupled to complementary bitline pairs, comprising:

(a) programming said DRAM to determine whether each bit of a plurality of bits should be stored in one cell or as opposite logic level bits in a pair of cells of said DRAM,

(b) applying each bit and its complement to a respective bitline pair of said DRAM,

(c) activating a wordline and storing said bit associated with said wordline in one cell or activating a pair of wordines and storing said bit and its complement in said pair of cells, depending on said programming.

2. A method of storing data in a DRAM array as defined in claim 1, comprising providing an unboosted wordline voltage Vdd and a boosted wordline voltage Vpp and selectably programming application of either of said voltages to a wordline prior to reading or writing of a bit to a charge storage cell associated with said wordline.

3. A method as defined in claim 2 in which said boosted wordline voltage Vpp is substantially equal to Vdd+Vtn, where Vtn is an n-channel field effect transistor (FET) conduction threshold.

4. A method as defined in claim 3 in which said boosted wordline voltage Vpp is generated by pumping up the normal wordline precharge voltage Vdd.

5. A method of storing data in a DRAM array as defined in claim 1, comprising providing an unboosted wordline voltage Vss and a boosted wordline precharge voltage Vpp and selectably programing application of either of said voltages to a wordline prior to reading or writing of a bit to a charge storage cell associated with said wordline.

6. A method as defined in claim 5 in which said boosted wordline voltage Vpp is substantially equal to Vss-Vtp, where Vtp is a p-channel field effect transistor (FET) conduction threshold.

7. A method as defined in claim 6 in which said boosted wordline voltage Vpp is generated by pumping down the normal wordline precharge voltage Vss.

8. A DRAM array comprising:

(a) plural wordlines and plural bitlines,

(b) bit charge storage capacitors associated with the bitlines and wordlines,

(c) cell access field effect transistors (FETs) having their gates connected to the wordlines and their source-drain circuits connected between the bitlines and the charge storage cells, for enabling reading or writing data from or to the charge storage capacitors,

(d) programmable addressing means for causing the wordlines, once addressed, to selectively enable either one or more than one cell access FET, whereby data can be selectively read from or written to one or more than one charge storage capacitor,

(e) a boosted wordline voltage source, and

(f) means for selectably connecting said boosted voltage source or an unboosted precharge voltage source to said wordlines, whereby said DRAM array can be operated selectably with or without a boosted wordline precharge voltage.

9. A DRAM array as defined in claim 8 in which said boosted wordline voltage source is comprised of a boosted voltage conductor, means connected to said conductor for detecting a level of said boosted voltage, an oscillator enabled by said detecting means, a level shifter for increasing the output voltage of said oscillator by a predetermined amount, and a pump for receiving an unboosted wordline voltage, the output voltage of the oscillator and the increased output voltage of the oscillator and increasing the unboosted wordline voltage and applying a resulting voltage to the conductor.

10. A DRAM as defined in claim 9, in which the output of the pump is substantially equal to the unboosted wordline voltage Vdd plus a field effect transistor (FET) conduction threshold voltage Vtn.