Electronic device and method for selective enabling of access to configuration registers used by a memory controller

• US 5,713,006 A
• Filed: 06/07/1995
• Issued: 01/27/1998
• Est. Priority Date: 03/15/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Shigeeda, Akio
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/478,163
• Time in Patent Office: 965 Days
• Field of Search: 395/497.01, 395/497.02, 395/497.03, 395/833, 395/830, 395/829, 395/828, 395/490, 395/494, 395/651, 395/653, 395/283, 395/285, 395/306, 395/309, 395/310, 395/700
• US Class Current: 711/170
• CPC Class Codes: G06F 1/1616 with folding flat displays, e.g. laptop computers or notebooks having a clamshell configuration, with body parts pivoting to an open position around an axis parallel to the plane they define in closed position
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

An electronic device and a method of operating the same to control access to configuration registers used by a memory controller, are disclosed. The disclosed device includes a single integrated circuit microprocessor unit that includes a microprocessor core, a memory controller circuit, a bus bridge circuit, and configuration registers. The microprocessor unit is connected to external dynamic random access memory (DRAM). The memory controller circuit is operable to perform an operation utilizing current information in one or more of the configuration registers. The bus bridge circuit includes a request logic circuit for supplying a request output signaling an impending access to one or more of the configuration registers. The memory controller circuit includes a reply logic circuit for supplying a reply output back to the request logic circuit after the operation utilizing current configuration register information is completed. The request logic includes an enable circuit responsive to the reply output to then enable the impending access to the configuration registers. The device is also disclosed as in a computer system that further includes integrated circuit devices, such as a direct memory access (DMA) circuit. The microprocessor unit may also include a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes circuitry for determining memory bank size and memory address type, as stored in the configuration registers.

Claims

1. An electronic device having a first plurality of terminals for external connection to a memory and a second plurality of terminals for external connection to a system bus, comprising:

a memory controller circuit coupled to said first plurality of terminals;

configuration registers for storing configuration information for use by said memory controller circuit in performing accesses to memory via said first plurality of terminals;

a bus bridge circuit coupled to said second plurality of terminals for transferring addresses and data, and comprising;

a request logic circuit for generating, responsive to at least one of the addresses, a write request signal to said memory controller circuit signaling an impending access to at least one of said configuration registers; and

an enable circuit for enabling a write access to at least one of said configuration registers responsive to receiving a reply signal;

wherein said memory controller circuit includes a reply logic circuit for generating the reply signal responsive to the combination of the write request signal from said request logic circuit and a signal in the memory controller indicating the absence of a pending memory operation utilizing current information in at least one of said configuration registers.

2. The device of claim 1, further comprising:

a microprocessor, coupled to the bus bridge circuit and to the memory controller, having a processing unit operable to process digital data in accordance with computer instructions, and implemented on a single integrated circuit with the memory controller circuit, configuration registers, and bus bridge circuit.

3. The device of claim 1, wherein the reply logic circuit comprises:

memory access logic circuitry, for generating a pending memory access signal responsive to the memory controller circuit issuing a memory access request signal or a memory refresh signal; and

reply signal generating logic, coupled to receive the pending memory access signal and the request signal, for generating the reply signal.

4. The device of claim 1 wherein configuration registers comprise locations for storing access controls for at least two addressable regions of an address space.

5. The device of claim 4 wherein said memory controller circuit further comprises a first selector logic circuit, responsive to at least some addresses transferred by said bus bridge circuit and responsive to said configuration register locations signifying access controls for the addressable regions, for producing a control signal to said bus bridge circuit.

6. The device of claim 5 further comprising:

a microprocessor, coupled to said memory controller circuit and to said bus bridge circuit, and operable to process digital data in accordance with computer instructions;

and wherein said memory controller circuit further comprises a second selector logic circuit, responsive to addresses asserted by said microprocessor and responsive to said configuration register locations signifying access controls for the addressable regions, for enabling memory access operations by said memory controller.

7. The device of claim 1 wherein said memory controller circuit further comprises:

cache status logic for generating a pending writeback signal responsive to receiving a signal indicating that at least one location of a cache memory contains modified data;

and wherein the reply logic circuit comprises;

memory access logic circuitry, for generating a pending memory access signal responsive to the memory controller circuit issuing a memory access request signal or a memory refresh signal, or to the cache status logic issuing the pending writeback signal; and

reply signal generating logic, coupled to receive the pending memory access signal and the write request signal, for generating the reply signal.

8. The device of claim 7 wherein said cache status logic receives the state of a plurality of dirty bits, each associated with a location of a cache memory, and generates the pending writeback signal responsive to all or one less than all of the plurality of dirty bits indicating that its associated location of cache memory contains modified data.

9. The device of claim 1, wherein the information stored by the configuration registers comprises memory access timing and memory address information, for use by the memory controller circuit in performing accesses to the memory.

10. The device of claim 9 wherein the configuration registers comprise a plurality of memory array type registers, each for storing a code indicating a column address width for a memory bank.

11. The device of claim 9, wherein the configuration registers comprise a timing control register, for storing a code indicating an access time of the memory.

12. The device of claim 9, wherein the configuration registers comprise a plurality of top memory address registers, each for storing a top memory address for an associated memory bank.

13. The device of claim 12, wherein the memory controller circuit comprises:

comparison circuitry, coupled to receive a memory address and to receive the contents of the top memory address registers, for selecting a memory bank responsive to the relationship of the memory address to the top memory addresses.

14. A method of operating an electronic device having a microprocessor, a memory controller for controlling access to a memory, and having configuration registers storing configuration information for use by the memory controller in accessing memory, comprising the steps of:

requesting a write access to one of the configuration registers;

monitoring the operation of the memory controller to detect whether a memory access is pending;

after the requesting step, and responsive to the monitoring step detecting a pending memory access utilizing current information in at least one of said configuration registers blocking write access to the configuration registers; and

after the requesting step, and responsive to the monitoring step detecting no pending memory access utilizing current information in at least one of said configuration registers, enabling write access to said configuration registers.

15. The method of claim 14, wherein the configuration registers comprise memory access timing and memory address information, for use in accessing memory.

16. The method of claim 15, wherein the configuration registers comprise a plurality of top memory address registers, each for storing a top memory address for an associated memory bank.

17. The method of claim 15, wherein the configuration registers comprise a plurality of memory array type registers, each for storing a code indicating a column address width for a memory bank.

18. The method of claim 15, wherein the configuration registers comprise a timing control register, for storing a code indicating an access time of the memory.

19. The method of claim 15, wherein the monitoring step comprises:

monitoring a first logic signal indicating whether a memory read/write access is pending; and

receiving a second logic signal indicating whether a memory refresh operation is pending.

20. The method of claim 19, wherein the monitoring step further comprises:

monitoring a third logic signal indicating whether a cache writeback operation is pending.