Method of making an ultra high density NAND gate using a stacked transistor arrangement

• US 5,714,394 A
• Filed: 11/07/1996
• Issued: 02/03/1998
• Est. Priority Date: 11/07/1996
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kadosh, Daniel, Gardner, Mark I.
• Primary Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/745,029
• Time in Patent Office: 453 Days
• Field of Search: 437/208, 437/21, 437/915, 437/51, 437/61, 437/62, 437/40 TFT, 437/41 TFT, 437/34, 437/57, 437/56, 148/DIG. 164, 257/347, 257/350, 257/351
• US Class Current: 438/199
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allows development of a high density NAND gate. The NAND gate includes two pairs of stacked transistors, wherein one transistor of a pair can be connected to the other transistor of that pair or connected to one or both transistors of the other pair.

Claims

1. A method for forming a NAND gate within an integrated circuit, comprising:

providing a first transistor having a first gate conductor arranged upon a first substrate between a first source implant and a first drain implant;

depositing a first interlevel dielectric upon the first source implant, upon the first drain implant and upon the first gate conductor;

forming an opening through said first interlevel dielectric to said first gate conductor;

filling said opening with a second gate conductor;

forming a gate dielectric upon said second gate conductor;

patterning a second substrate upon said gate dielectric;

implanting a second source implant and a second drain implant into said second substrate to form a second transistor;

depositing a second interlevel dielectric upon and laterally adjacent said second transistor;

repeating the above steps to form a third transistor and a fourth transistor; and

interconnecting said first transistor in series with said third transistor and

interconnecting said second transistor in parallel with said fourth transistor to form said NAND gate.

2. The method as recited in claim 1, further comprising interconnecting the first transistor with the second transistor by forming an output conductor of the NAND gate which extends through said first and second interlevel dielectrics and abuts against both said first and second drain implants, while simultaneously forming a power conductor of said NAND gate which extends through said first interlevel dielectric to said second source implant.

3. The method as recited in claim 1, wherein said first substrate comprises substantially single crystalline silicon, and wherein said second substrate comprises substantially polycrystalline silicon.

4. The method as recited in claim 1, wherein said first and third transistor comprise NMOS transistors, and said second and fourth transistors comprise PMOS transistors.

5. The method as recited in claim 2, wherein said forming the output conductor comprises removing said first and second interlevel dielectrics along an axis perpendicular to an upper surface of said first substrate to expose a lateral surface of said second substrate and an upper surface of said first drain implant.

6. The method as recited in claim 2, wherein said output conductor and said power conductor extend substantially parallel to each other.

7. The method as recited in claim 1, further comprising forming a silicide upon said first source implant, said first drain implant and said first gate conductor prior to said depositing the first interlevel dielectric.

8. The method as recited in claim 1, wherein said forming the gate dielectric comprises thermally growing an oxide upon said second gate conductor.

9. The method as recited in claim 1, further comprising providing a well-connect implant within said first substrate a spaced distance from said first drain and source implants.