×

Method of making an ultra high density NAND gate using a stacked transistor arrangement

  • US 5,714,394 A
  • Filed: 11/07/1996
  • Issued: 02/03/1998
  • Est. Priority Date: 11/07/1996
  • Status: Expired due to Term
First Claim
Patent Images

1. A method for forming a NAND gate within an integrated circuit, comprising:

  • providing a first transistor having a first gate conductor arranged upon a first substrate between a first source implant and a first drain implant;

    depositing a first interlevel dielectric upon the first source implant, upon the first drain implant and upon the first gate conductor;

    forming an opening through said first interlevel dielectric to said first gate conductor;

    filling said opening with a second gate conductor;

    forming a gate dielectric upon said second gate conductor;

    patterning a second substrate upon said gate dielectric;

    implanting a second source implant and a second drain implant into said second substrate to form a second transistor;

    depositing a second interlevel dielectric upon and laterally adjacent said second transistor;

    repeating the above steps to form a third transistor and a fourth transistor; and

    interconnecting said first transistor in series with said third transistor andinterconnecting said second transistor in parallel with said fourth transistor to form said NAND gate.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×