Method of making a transistor having a deposited dual-layer spacer structure

• US 5,714,413 A
• Filed: 12/11/1995
• Issued: 02/03/1998
• Est. Priority Date: 12/11/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hussein, Makarem A., Brigham, Lawrence N., Cotner, Raymond E.
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US08/570,726
• Time in Patent Office: 785 Days
• Field of Search: 437/44, 437/40 SW, 437/41 SW, 438/301, 438/303, 438/305
• US Class Current: 438/301
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A transistor comprising a deposited dual-layer spacer structure and method of fabrication. A polysilicon layer is deposited over a gate dielectric, and is subsequently etched to form the polysilicon gate electrode of the transistor. Next, oxide is deposited over the surface of the gate electrode, followed by deposition of a second dielectric layer. Spacers are then formed adjacent to the gate electrode by etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the oxide.

Claims

1. A method of forming a transistor, comprising the steps of:

a. forming a gate electrode over a dielectric;

b. depositing a first dielectric layer over the gate electrode, the first dielectric layer comprising an oxide;

c. depositing a second dielectric layer over the first dielectric layer;

d. etching back the second dielectric layer using a substantially anisotropic etch, thereby forming an upper region of a spacer, said spacer adjacent to the gate electrode; and

e. forming a doped region adjacent to said gate electrode such that said doped region is formed prior to the deposition of said first and second dielectric layers.

2. The method of claim 1, further comprising the steps of implanting a tip region of a first dose after forming the gate electrode, and implanting a source/drain region of a second dose after etching back the second dielectric layer, the first dose being approximately within 1.5 orders of magnitude of the first second dose.

3. The method of claim 1, further comprising the step of etching back the first dielectric layer after etching back the second dielectric layer.

4. The method of claim 1, further comprising the step of oxidizing the gate electrode before depositing the first dielectric layer, thereby forming a reox layer.

5. The method of claim 4, further comprising the steps of implanting a tip region of a first dose after forming the gate electrode, and implanting a source/drain region of a second dose after etching back the second dielectric layer, the first dose being at least 1.5 orders of magnitude less than the second dose.

6. The method of claim 4, further comprising the step of etching back the first dielectric layer and the reox layer after etching back the second dielectric layer.

7. The method of claim 1, wherein the second dielectric layer comprises a nitride.

8. The method of claim 1, wherein the first dielectric layer has a thickness in the range of approximately 50 Å

to 300 Å

, and the second dielectric layer has a thickness in the range of approximately 800 Å

to 3000 Å

.

9. The method of claim 4, wherein the reox layer has a thickness in the range of approximately 50 Å

, to 500 Å

, the first dielectric layer has a thickness in the range of approximately 50 Å

, to 300 Å

, and the second dielectric layer has a thickness in the range of approximately 800 Å

to 3000 Å

.

10. The method of claim 2, wherein the tip region and the source/drain region are both implanted with arsenic.

11. The method of claim 2, wherein the tip region and the source/drain region are implanted with a material selected from the group consisting of arsenic, phosphorus, antimony, and boron.

12. A method of forming a transistor, comprising the steps of:

a. forming a gate electrode over a gate dielectric, the gate electrode comprising polysilicon;

b. depositing a first dielectric layer directly on the gate electrode, the first dielectric layer comprising an oxide;

c. depositing a second dielectric layer directly on the first dielectric layer, the second dielectric layer comprising nitride;

d. etching back the second dielectric layer using a substantially anisotropic etch, thereby forming an upper region of a spacer, said spacer adjacent to the gate electrode; and

e. forming a doped region adjacent to said gate electrode such that said doped region is formed prior to the deposition of said first and second dielectric layers.

13. The method of claim 12, further comprising the steps of implanting a first dose of a first dopant in a tip region after forming the gate electrode, and implanting a second dose of a second dopant in a source/drain region after etching back the second dielectric layer, the first dose being within approximately 1.5 orders of magnitude of the second dose, the first and second dopants being selected from a group consisting of arsenic, phosphorous, antimony, and boron.

14. The method of claim 12, further comprising the steps of implanting a tip region of a first dose after forming the gate electrode, and implanting a source/drain region of a second dose after etching back the second dielectric layer, the first dose being less than approximately 1.5 orders of magnitude of the second dose.

15. The method of claim 12, wherein the first dielectric layer has a thickness in the range of approximately 50 Å

to 300 Å

, and the second dielectric layer has a thickness in the range of approximately 800 Å

to 3000 Å

.

16. The method of claim 12, wherein the first dielectric layer, comprising oxide, is deposited by a chemical vapor deposition process, and the second dielectric layer, comprising nitride, is deposited by a plasma-enhanced chemical vapor deposition process.

17. A method of forming a transistor, comprising the steps of:

a. depositing a polysilicon layer over a gate dielectric;

b. etching the polysilicon layer to form a polysilicon gate electrode;

c. implanting a first dose of a first dopant to form a tip region;

d. depositing a first dielectric layer directly on the polysilicon gate electrode, after forming said tip region, the first dielectric layer being oxide;

e. depositing a second dielectric layer directly on the first dielectric layer, the second dielectric layer being nitride;

f. etching back the second dielectric layer using a substantially anisotropic etch, thereby forming an upper region of a spacer, said spacer adjacent to the polysilicon gate electrode; and

g. implanting a second dose of a second dopant to form a source/drain region.

18. The method of claim 17, further comprising the step of isotropically etching back the first dielectric layer using a wet etch.

19. The method of claim 17, wherein the first dose is within approximately 1.5 orders of magnitude of the second dose, and the first and second dopants are selected from a group consisting of arsenic, phosphorous, antimony, and boron.

20. The method of claim 17, wherein the first dose is less than approximately 1.5 orders of magnitude of the second dose, and the first and second dopants are selected from a group consisting of arsenic, phosphorous, antimony, and boron.

21. The method of claim 17, wherein the first dielectric layer has a thickness in the range of approximately 50 Å

, to 150 Å

, and the second dielectric layer has a thickness in the range of approximately 500 Å

to 2500 Å

.

22. The method of claim 17, wherein the second dielectric layer is deposited by a plasma-enhanced chemical vapor deposition process.

23. A method of forming a transistor, comprising the steps of:

a. forming a gate electrode over a dielectric;

b. depositing a first undoped dielectric layer over the gate electrode, the first dielectric layer comprising an oxide;

c. depositing a second dielectric layer over the first dielectric layer; and

d. etching back the second dielectric layer using a substantially anisotropic etch, thereby forming an upper region of a spacer, said spacer adjacent to the gate electrode;

e. forming a doped region adjacent to said gate electrode such that said doped region is formed prior to the deposition of said first and second dielectric layers.