Semiconductor device having a gate electrode in a grove and a diffused region under the grove
First Claim
1. A semiconductor device comprising:
- a semiconductor substrate having a first conductivity type semiconductor region at a main surface thereof, said semiconductor substrate having within said semiconductor region a concave portion which has a bottom surface and a sidewall surface;
a body region of a second conductivity type formed within said semiconductor region and in contact with said sidewall surface of said concave portion;
a source region of said first conductivity type formed within said body region, wherein a channel region is defined at said sidewall surface of said concave portion by a portion of said body region between said source region and said semiconductor region;
a gate insulating film disposed to cover said sidewall surface and said bottom surface of said concave portion;
a gate electrode disposed on said concave portion to be insulated with said gate insulating film; and
an impurity diffusion region disposed at said bottom surface of said concave portion;
wherein said gate insulating film covering said bottom surface of said concave portion has a distribution in thickness thereof such that a thickness becomes thicker closer to a central portion of said bottom surface of said concave portion, and a thickness of said gate insulating film at said central portion of said bottom surface of said concave portion is controlled to be thicker than a thickness of said gate insulating film at said sidewall surface of said concave portion.
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Accused Products
Abstract
A power MOSFET having a groove for forming a channel improved for shortening the switching time and increasing the dielectric breakdown strength of the gate oxide film is disclosed. The power MOSFET includes a concave structure in which a gate oxide film at a groove bottom is thickened. Namely, since the gate oxide film between a gate electrode and a first conductivity type semiconductor layer is thick, the capacitance of the oxide film therebetween is reduced. Therefore, the input and output capacitance of the gate oxide film can be reduced, and switching loss can be also reduced since the switching time can be shortened. Further, greater dielectric breakdown strength of the gate oxide film can be obtained as a result of the thickened gate oxide film at the groove bottom.
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Citations
25 Claims
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1. A semiconductor device comprising:
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a semiconductor substrate having a first conductivity type semiconductor region at a main surface thereof, said semiconductor substrate having within said semiconductor region a concave portion which has a bottom surface and a sidewall surface; a body region of a second conductivity type formed within said semiconductor region and in contact with said sidewall surface of said concave portion; a source region of said first conductivity type formed within said body region, wherein a channel region is defined at said sidewall surface of said concave portion by a portion of said body region between said source region and said semiconductor region; a gate insulating film disposed to cover said sidewall surface and said bottom surface of said concave portion; a gate electrode disposed on said concave portion to be insulated with said gate insulating film; and an impurity diffusion region disposed at said bottom surface of said concave portion; wherein said gate insulating film covering said bottom surface of said concave portion has a distribution in thickness thereof such that a thickness becomes thicker closer to a central portion of said bottom surface of said concave portion, and a thickness of said gate insulating film at said central portion of said bottom surface of said concave portion is controlled to be thicker than a thickness of said gate insulating film at said sidewall surface of said concave portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor device comprising:
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a semiconductor substrate having an n-type semiconductor region at a main surface thereof, said semiconductor substrate having within said semiconductor region a concave portion which has a bottom surface and a sidewall surface; a body region of a p-type formed within said semiconductor region and in contact with said sidewall surface of said concave portion; a source region of said n-type formed within said body region, wherein a channel region is defined at said sidewall surface of said concave portion by a portion of said body region between said source region and said semiconductor region; a gate insulating film disposed to cover said sidewall surface and said bottom surface of said concave portion; a gate electrode disposed on said concave portion insulated with said gate insulating film; and an impurity diffusion region disposed at said bottom surface of said concave portion; said gate insulating film covering said bottom surface of said concave portion having a distribution in thickness thereof such that a thickness becomes thicker closer to a central portion of said bottom surface of said concave portion, and a thickness of said gate insulating film at said central portion of said bottom surface of said concave portion is controlled to be thicker than a thickness of said gate insulating film at said sidewall surface of said concave portion. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A semiconductor device comprising:
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a semiconductor substrate having a first conductivity type semiconductor region at a main surface thereof oriented in a (100) plane, said semiconductor substrate having within said semiconductor region a concave portion which has a bottom surface and a sidewall surface; a body region of a second conductivity type formed up to a depth deeper than a depth of said concave portion within said semiconductor region and in contact with said sidewall surface of said concave portion; a source region of said first conductivity type formed within said body region, wherein a channel region is defined at said sidewall of said concave portion by a portion of said body region between said source region and said semiconductor region; a gate insulating film disposed to cover an inlet portion, said sidewall surface and said bottom surface of said concave portion; and a gate electrode disposed on said concave portion insulated with said gate insulating film; a thickness of said gate insulating film between said gate electrode and said sidewall surface of said concave portion being thinner than a thickness of said gate insulating film between said gate electrode and said inlet portion of said concave portion; said gate insulating film covering said bottom surface of said concave portion having a distribution in thickness thereof such that a thickness becomes thicker closer to a central portion of said bottom surface of said concave portion; and an impurity diffusion region disposed at said bottom surface of said concave portion. - View Dependent Claims (21, 22, 23, 24, 25)
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Specification