Semiconductor device having a gate electrode in a grove and a diffused region under the grove

• US 5,714,781 A
• Filed: 04/26/1996
• Issued: 02/03/1998
• Est. Priority Date: 04/27/1995
• Status: Expired due to Term

• Current Assignee: Nippondenso Co., Ltd. (DENSO Corporation)
• Original Assignee: Nippondenso Co., Ltd. (DENSO Corporation)
• Inventors: Yamamoto, Tsuyoshi, Fukazawa, Takeshi, Naito, Masami
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Abraham, Fetsum
• Application Number:
  US08/638,388
• Time in Patent Office: 648 Days
• Field of Search: 257/329, 257/330, 257/333, 257/389, 257/397, 257/341, 257/263
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET having a groove for forming a channel improved for shortening the switching time and increasing the dielectric breakdown strength of the gate oxide film is disclosed. The power MOSFET includes a concave structure in which a gate oxide film at a groove bottom is thickened. Namely, since the gate oxide film between a gate electrode and a first conductivity type semiconductor layer is thick, the capacitance of the oxide film therebetween is reduced. Therefore, the input and output capacitance of the gate oxide film can be reduced, and switching loss can be also reduced since the switching time can be shortened. Further, greater dielectric breakdown strength of the gate oxide film can be obtained as a result of the thickened gate oxide film at the groove bottom.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first conductivity type semiconductor region at a main surface thereof, said semiconductor substrate having within said semiconductor region a concave portion which has a bottom surface and a sidewall surface;

a body region of a second conductivity type formed within said semiconductor region and in contact with said sidewall surface of said concave portion;

a source region of said first conductivity type formed within said body region, wherein a channel region is defined at said sidewall surface of said concave portion by a portion of said body region between said source region and said semiconductor region;

a gate insulating film disposed to cover said sidewall surface and said bottom surface of said concave portion;

a gate electrode disposed on said concave portion to be insulated with said gate insulating film; and

an impurity diffusion region disposed at said bottom surface of said concave portion;

wherein said gate insulating film covering said bottom surface of said concave portion has a distribution in thickness thereof such that a thickness becomes thicker closer to a central portion of said bottom surface of said concave portion, and a thickness of said gate insulating film at said central portion of said bottom surface of said concave portion is controlled to be thicker than a thickness of said gate insulating film at said sidewall surface of said concave portion.

2. A semiconductor device according to claim 1, wherein:

a depth of said concave portion is selected to be shallower than a junction depth of said body region.

3. A semiconductor device according to claim 1, wherein:

said semiconductor substrate is silicon; and

said main surface of said semiconductor substrate is oriented in a (100) plane.

4. A semiconductor device according to claim 3, wherein:

an elevation angle of said sidewall surface with respect to said main surface of said semiconductor substrate is selected such that said sidewall surface is substantially oriented in a (111) plane.

5. A semiconductor device according to claim 1, wherein:

said gate insulating film is further disposed on said main surface of said semiconductor substrate covering an inlet portion of said concave portion.

6. A semiconductor device according to claim 5, wherein:

said gate insulating film disposed on said main surface of said semiconductor substrate has a thickness thicker than said gate insulating film at a portion of said sidewall surface where said channel region is disposed.

7. A semiconductor device according to claim 1, wherein:

said impurity diffusion region has said first conductive type and an impurity concentration higher than an impurity concentration of said semiconductor region.

8. A semiconductor device according to claim 7, wherein:

said impurity diffusion region is disposed to be apart from said body region.

9. A semiconductor device according to claim 1, wherein:

said impurity diffusion region is a region which is implanted with an impurity of neither n-type dopant nor p-type dopant.

10. A semiconductor device according to claim 9, wherein said impurity implanted into said region is any one of:

N-ion;

Si-ion; and

O-ion.

11. A semiconductor device comprising:

a semiconductor substrate having an n-type semiconductor region at a main surface thereof, said semiconductor substrate having within said semiconductor region a concave portion which has a bottom surface and a sidewall surface;

a body region of a p-type formed within said semiconductor region and in contact with said sidewall surface of said concave portion;

a source region of said n-type formed within said body region, wherein a channel region is defined at said sidewall surface of said concave portion by a portion of said body region between said source region and said semiconductor region;

a gate insulating film disposed to cover said sidewall surface and said bottom surface of said concave portion;

a gate electrode disposed on said concave portion insulated with said gate insulating film; and

an impurity diffusion region disposed at said bottom surface of said concave portion;

said gate insulating film covering said bottom surface of said concave portion having a distribution in thickness thereof such that a thickness becomes thicker closer to a central portion of said bottom surface of said concave portion, and a thickness of said gate insulating film at said central portion of said bottom surface of said concave portion is controlled to be thicker than a thickness of said gate insulating film at said sidewall surface of said concave portion.

12. A semiconductor device according to claim 11, wherein:

said depth of said concave portion is shallower than a junction depth of said body region.

13. A semiconductor device according to claim 12, wherein:

said impurity diffusion region is a region implanted with an impurity of As-ion.

14. A semiconductor device according to claim 11, wherein:

said semiconductor substrate is silicon; and

said main surface of said semiconductor substrate is oriented in a (100) plane.

15. A semiconductor device according to claim 14, wherein:

an elevation angle of said sidewall surface with respect to said main surface of said semiconductor substrate is selected such that said sidewall surface is substantially oriented in a (111) plane.

16. A semiconductor device according to claim 11, wherein:

said gate insulating film is further disposed on said main surface of said semiconductor substrate covering an inlet portion of said concave portion.

17. A semiconductor device according to claim 16, wherein:

said gate insulating film disposed on said main surface of said semiconductor layer has a thickness thicker than said gate insulating film at said sidewall portion where said channel region is disposed.

18. A semiconductor device according to claim 11, wherein:

said impurity diffusion region has said n-type and an impurity concentration higher than an impurity concentration of said semiconductor region.

19. A semiconductor device according to claim 18, wherein:

said impurity diffusion region is disposed to be apart from said body region.

20. A semiconductor device comprising:

a semiconductor substrate having a first conductivity type semiconductor region at a main surface thereof oriented in a (100) plane, said semiconductor substrate having within said semiconductor region a concave portion which has a bottom surface and a sidewall surface;

a body region of a second conductivity type formed up to a depth deeper than a depth of said concave portion within said semiconductor region and in contact with said sidewall surface of said concave portion;

a source region of said first conductivity type formed within said body region, wherein a channel region is defined at said sidewall of said concave portion by a portion of said body region between said source region and said semiconductor region;

a gate insulating film disposed to cover an inlet portion, said sidewall surface and said bottom surface of said concave portion; and

a gate electrode disposed on said concave portion insulated with said gate insulating film;

a thickness of said gate insulating film between said gate electrode and said sidewall surface of said concave portion being thinner than a thickness of said gate insulating film between said gate electrode and said inlet portion of said concave portion;

said gate insulating film covering said bottom surface of said concave portion having a distribution in thickness thereof such that a thickness becomes thicker closer to a central portion of said bottom surface of said concave portion; and

an impurity diffusion region disposed at said bottom surface of said concave portion.

21. A semiconductor device according to claim 20, wherein:

said semiconductor substrate is silicon; and

said main surface of said semiconductor substrate is oriented in a (100) plane.

22. A semiconductor device according to claim 21, wherein:

an elevation angle of said sidewall surface with respect to said main surface of said semiconductor substrate is selected such that said sidewall surface is substantially oriented in a (111) plane.

23. A semiconductor device according to claim 20, wherein:

said impurity diffusion region has said first conductive type and an impurity concentration higher than an impurity concentration of said semiconductor region.

24. A semiconductor device according to claim 23, wherein:

said impurity diffusion region is disposed to be apart from said body region.

25. A semiconductor device according to claim 20, wherein:

said impurity diffusion region is a region implanted with an impurity of neither n-type dopant nor p-type dopant.