Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors

• US 5,714,786 A
• Filed: 10/31/1996
• Issued: 02/03/1998
• Est. Priority Date: 10/31/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kao, David, Gonzalez, Fernando
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US08/741,828
• Time in Patent Office: 460 Days
• Field of Search: 257/296, 257/365-367, 257/344
• US Class Current: 257/366
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

An improved transistor structure includes an insulated conductive gate spacer which is contacted and driven separately from the gate of the transistor. The gate spacer serves as a control or second gate for the transistor and may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistor are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors. When the improved transistor is used selectively within an integrated circuit, the remaining devices can be structured as standard LDD transistors using the gate spacers in a conventional manner.

Claims

1. A transistor structure comprising:

a gate structure formed on a first oxide layer on a silicon structure;

a secondary oxide layer formed on said gate structure;

a conductive spacer formed around said gate structure on said secondary oxide layer, said conductive spacer including an aperture over a portion of said gate structure;

a first contact to said gate structure through said portion of said gate structure corresponding to said aperture; and

a second contact to said conductive spacer.

2. A transistor structure as claimed in claim 1 wherein said gate structure comprises a gate and a conductive spacer connection support separated from said gate wherein said portion of said gate structure corresponding to said aperture is a portion of said gate, and said second contact is made at said conductive spacer connection support.

3. A transistor structure as claimed in 1 wherein said gate structure comprises a wordline.

4. A transistor structure as claimed in 1 wherein said gate structure comprises a multilayer structure.

5. A dual gate transistor structure comprising:

a gate structure formed on a first oxide layer on a silicon structure and defining a first gate;

a secondary oxide layer formed over said gate structure;

a conductive spacer formed around said gate structure on said secondary oxide layer, said conductive spacer defining a second gate and including an aperture over a portion of said gate structure;

a first contact to said first gate through said portion of said gate structure corresponding to said aperture; and

a second contact to said conductive spacer.

6. A transistor structure comprising:

an actual gate and a pseudo gate formed on a first oxide layer on a silicon structure, said actual and pseudo gates being separated from one another;

a secondary oxide layer formed over said actual and pseudo gates;

a conductive spacer formed around said actual and pseudo gates on said secondary oxide layer, said conductive spacer including an aperture over a portion of said actual gate;

a first contact to said actual gate through said portion of said actual gate corresponding to said aperture; and

a second contact to said conductive spacer at said pseudo gate.

7. A method of making a transistor structure comprising the steps of:

forming a gate structure on a first oxide layer on a silicon structure;

forming a secondary oxide layer on said gate structure;

forming a conductive spacer around said gate structure on said secondary oxide layer;

removing said conductive spacer from a portion of said gate structure;

forming a first contact to said gate structure through said portion of said gate structure from which said conductive spacer has been removed; and

forming a second contact to said conductive spacer.

8. A method of making a transistor structure comprising the steps of:

forming a gate on a first oxide layer on a silicon structure;

forming a conductive spacer connection support on said first oxide layer on said silicon structure but separated from said gate;

forming a secondary oxide layer on said gate and said conductive spacer connection support;

forming a conductive spacer around said gate and said conductive spacer connection support on said secondary oxide layer;

removing said conductive spacer from a portion of said gate;

forming a first contact to said gate through said portion of said gate structure from which said conductive spacer has been removed; and

forming a second contact to said conductive spacer at said conductive spacer connection support.

9. A method of making a dual gate transistor structure comprising the steps of:

forming a gate structure on a first oxide layer on a silicon structure to define a first gate;

forming a secondary oxide layer over said gate structure;

forming a conductive spacer around said gate structure on said secondary oxide layer to define a second gate;

removing said conductive spacer from a portion of said gate structure;

forming a first contact to said first gate through said portion of said gate structure from which said conductive spacer has been removed; and

forming a second contact to said conductive spacer.

10. A method of making a transistor structure comprising the steps of:

forming an actual gate on a first oxide layer on a silicon structure;

forming a pseudo gate on said first oxide layer on said silicon structure;

forming a secondary oxide layer over said actual gate and said pseudo gate;

forming a conductive spacer around said actual gate and said pseudo gate on said secondary oxide layer;

removing said conductive spacer from a portion of said actual gate;

forming a first contact to said actual gate through said portion of said actual gate from which said conductive spacer has been removed; and

forming a second contact to said conductive spacer at said pseudo gate.

11. An integrated circuit structure comprising:

a first plurality of conventional LDD transistors; and

a second plurality of transistors each comprising;

a gate structure formed on a first oxide layer on a silicon structure;

a secondary oxide layer formed on said gate structure;

a conductive spacer formed around said gate structure on said secondary oxide layer, said conductive spacer including an aperture over a portion of said gate structure;

a first contact to said gate structure through said portion of said gate structure corresponding to said aperture; and

a second contact to said conductive spacer, said first plurality of conventional LDD transistors and said second plurality of transistors being interconnected to form said integrated circuit structure.

12. An integrated circuit structure as claimed in claim 11 wherein said integrated circuit structure is an array device.

13. An integrated circuit structure as claimed in claim 11 wherein said integrated circuit structure is a storage device.

14. A method of making an integrated circuit structure comprising the steps of:

forming gate structures on a first oxide layer on a silicon structure;

forming a secondary oxide layer on said gate structures;

forming conductive spacers around said gate structures;

utilizing said conductive spacers to form LDD transistor structures associated with a first number of said gate structures;

utilizing said conductive spacers to form transistor structures associated with a second number of said gate structures by performing the steps of;

removing said conductive spacer from portions of said second number of said gate structures;

forming first contacts to said second number of gate structures through said portions of said second number of gate structures from which said conductive spacer has been removed; and

forming second contacts to said conductive spacers.