Three state switch detection using current sensing

• US 5,714,852 A
• Filed: 09/13/1996
• Issued: 02/03/1998
• Est. Priority Date: 09/13/1996
• Status: Expired due to Term

• Current Assignee: Lear Corporation Eeds & Interiors (Rtx Corporation)
• Original Assignee: United Technologies Automotive, Inc. (Lear Corporation)
• Inventors: Enderich, Mark A.
• Primary Examiner(s): Ro, Bentsu
• Application Number:
  US08/713,475
• Time in Patent Office: 508 Days
• Field of Search: 318/256, 318/264, 318/265, 318/266, 318/280, 318/286, 318/287, 318/291, 318/293, 318/112, 318/543
• US Class Current: 318/256
• CPC Class Codes: B60R 1/07 by electrically powered actuators
• CPC Class Codes: H01H 9/167 Circuits for remote indication
• CPC Class Codes: H03M 5/16 the pulses having three levels

Abstract

A three state switch detection circuit converts a three state input to a two-bit binary output readable by a micro-controller or other digital logic. The circuit utilized complementary NPN and PNP transistors having coupled emitters and coupled bases connected by a resistor. The collector of the PNP transistor is connected by a resistor to ground while a complementary resistor ties the collector of the NPN transistor to V_BATT. Additional circuitry preferably converts the voltage output from the collectors to a suitable voltage level readable by the micro-controller or other digital logic device.

Claims

1. A circuit for converting a three state input to a two-bit binary output comprising:

a first switch connecting a first output to said input when said input is high, said first output connected to a first reference voltage; and

a second switch connecting a second output to said input when said input is low, said second output connected to a second reference voltage.

2. The circuit of claim 1 wherein said first output is substantially equal to said first reference voltage when said input is an open circuit and said second output is substantially equal to said second reference voltage when said input is an open circuit.

3. The circuit of claim 1 wherein said first output is connected to ground by a resistor.

4. The circuit of claim 1 wherein said second output is connected to a positive voltage by a resistor.

5. The circuit of claim 1 wherein said switches are transistors.

6. The circuit of claim 1 wherein said switches are complementary transistors.

7. The circuit of claim 1 wherein said first switch is a pnp transistor and said second switch is an npn transistor,

said pnp transistor having a first emitter, a first base and a first collector, said first collector and said first base are coupled to a reference voltage;

said npn transistor having a second emitter, a second base and a second collector, said second emitter coupled to said first emitter of said pnp transistor, said second base coupled to said reference voltage; and

said bases of said transistors being connected to said emitters of said transistors.

8. The circuit of claim 7 wherein said first base is connected to said second base.

9. A circuit for controlling a motor-driven feature in a vehicle comprising:

a first motor for operating a motor-driven feature, said first motor having a first input line and a second input line;

a user switch for operating said first motor, said user switch having a low state, a high state and an open state;

a tri-state detection circuit receiving a tri-state signal from said user switch and converting said tri-state signal into a two-bit binary signal, said two-bit binary signal comprising a first bit and a second bit indicating the state of said user switch, said tri-state detection circuit including a first switch and a second switch, said first switch connecting said first bit to said user switch when said user switch is in said high state, said second switch connecting said second bit to said user switch when said user switch is in said low state; and

a controller receiving said two-bit binary signal from said tri-state detection circuit, said controller operating said first motor to a stored setting for said motor-driven feature only when said two-bit binary signal indicates that said user switch is in said open state.

10. The circuit of claim 9 wherein said first bit is connected to a first reference voltage and said second bit is connected to a second reference voltage.

11. The circuit of claim 9 wherein said first switch is a pnp transistor and said second switch is an npn transistor,

said pnp transistor having a first emitter, a first base and a first collector, said first collector and said first base are coupled to a reference voltage;

said npn transistor having a second emitter, a second base and a second collector, said second emitter coupled to said first emitter of said pnp transistor, said second base coupled to said reference voltage; and

said bases of said transistors being connected to said emitters of said transistors by at least one resistor.

12. The circuit of claim 11 wherein said first collector is connected to ground by a first resistor, said second collector connected to a positive voltage by a second resistor.

13. The circuit of claim 11 wherein said first base is connected to said second base.

14. A method for converting a three state input to a two-bit binary output including the steps of:

connecting said input to a first output when said input is high;

connecting said input to a second output when said input is low;

connecting said first output to a first reference voltage when said input is low;

connecting said first output to said first reference voltage when said input is open;

connecting said second output to a second reference voltage when said output is high; and

connecting said second output to said second reference voltage when said output is open.

15. The method of claim 14 further including the steps of:

connecting an emitter of a pnp transistor to said input, connecting a collector of said pnp transistor to ground by a first resistor; and

connecting an emitter of an npn transistor to said input, connecting said emitter of said npn transistor to said emitter of said pnp transistor, connecting a base of said npn transistor to a base of said pnp transistor, connecting said bases of said transistors to said emitters of said transistors by a second resistor, connecting a collector of said npn transistor to a reference voltage by a resistor.