Constant transductance input stage and integrated circuit implementations thereof
First Claim
1. A method for operating an integrated circuit to enhance the consistency of transconductance exhibited by it, said circuit comprising a differential input stage having at least a first transistor pair of a first conductivity type providing a first output in response to an applied input signal and having at least a second transistor pair of a second conductivity type electrically coupled in parallel with said first transistor pair and responsive to said applied input to provide a second output, said method comprising the steps of:
- simultaneously processing said first and second outputs with respect to the amplitudes exhibited thereby;
selecting that instantaneously occurring one of said first output or said second output exhibiting the highest amplitude to provide a selected output; and
applying said selected output corresponding with said highest amplitude, to a next stage of said integrated circuit.
1 Assignment
0 Petitions
Accused Products
Abstract
A low voltage constant transconductance input stage is achieved with relatively simple design methodology. The approach uses current-mode techniques and is based upon the processing of signal currents, rather than handling the bias currents of input stages. Such an approach becomes universal and independent of the input stage transistor types (FET or bipolar) and their operating regions. Further, the arrangement considerably simplifies the design procedure of low voltage operational amplifiers. MOS and bipolar Op Amp input stages are described wherein almost constant gm is achieved which is independent of the common mode input voltage ranging from rail-to-rail.
-
Citations
24 Claims
-
1. A method for operating an integrated circuit to enhance the consistency of transconductance exhibited by it, said circuit comprising a differential input stage having at least a first transistor pair of a first conductivity type providing a first output in response to an applied input signal and having at least a second transistor pair of a second conductivity type electrically coupled in parallel with said first transistor pair and responsive to said applied input to provide a second output, said method comprising the steps of:
-
simultaneously processing said first and second outputs with respect to the amplitudes exhibited thereby; selecting that instantaneously occurring one of said first output or said second output exhibiting the highest amplitude to provide a selected output; and applying said selected output corresponding with said highest amplitude, to a next stage of said integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. An integrated circuit, comprising:
-
a differential stage having at least an n-type transistor pair and at least a p-type transistor pair, said n-type and p-type transistor pairs being electrically coupled in parallel and responsive to an applied input to respectively provide corresponding first and second current outputs which are common mode voltage dependent; and a selection circuit responsive to said current outputs and providing a selected current output corresponding with the first and second current output which exhibits a maximum current amplitude and maximum stage transconductance as an input to a next stage of said integrated circuit. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
-
-
20. An integrated circuit, comprising:
-
a differential stage having an n-type transistor pair and a p-type transistor pair, said n-type and p-type transistor pairs having a bias current, IB, applied thereto and being electrically coupled in parallel and responsive to an applied input to provide respective current outputs In1, In2, and Ip1, Ip2 corresponding with said applied input and combined with a DC term; a processing circuit for subtracting said current outputs In1, In2, Ip1 and Ip2 from said bias current, IB to provide respective subtracted currents In1'"'"', In2'"'"', Ip1'"'"' and Ip2'"'"' each exhibiting said or another DC term; a first selector circuit responsive to said subtracted currents In1'"'"' and Ip1'"'"' for providing an initial output Io2 corresponding with a minimum amplitude of simultaneously occurring said subtracted currents In1'"'"' and Ip1'"'"'; and a second selector circuit responsive to said subtracted currents In2'"'"' and Ip2'"'"' for providing an initial output Io1 corresponding with a minimum amplitude of simultaneously occurring said subtracted currents In2'"'"' and Ip2'"'"'. - View Dependent Claims (21, 22, 23, 24)
-
Specification