Constant transductance input stage and integrated circuit implementations thereof

• US 5,714,906 A
• Filed: 08/14/1995
• Issued: 02/03/1998
• Est. Priority Date: 08/14/1995
• Status: Expired due to Fees

• Current Assignee: Chipworks Incorporated
• Original Assignee: Chipworks Incorporated
• Inventors: Motamed, Ali, Hwang, Chang Ku, Ismail, Mohammed
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US08/514,910
• Time in Patent Office: 904 Days
• Field of Search: 330/253, 330/257, 327/563, 327/562, 327/561, 327/560, 327/62, 327/63, 327/58
• US Class Current: 327/563
• CPC Class Codes: H03F 2200/162 FETs are biased in the weak inversion region
• CPC Class Codes: H03F 2203/45371 the AAC comprising parallel coupled multiple transistors at their source and gate and drain or at their base and emitter and collector, e.g. in a cascode dif amp, only those forming the composite common source transistor or the composite common emitter transistor respectively
• CPC Class Codes: H03F 2203/45388 the AAC comprising diodes in the source circuit of the AAC before the common source coupling
• CPC Class Codes: H03F 2203/45392 the AAC comprising resistors in the source circuit of the AAC before the common source coupling
• CPC Class Codes: H03F 3/3023 with asymmetrical driving of the end stage
• CPC Class Codes: H03F 3/3067 with asymmetrical driving of the end stage
• CPC Class Codes: H03F 3/45112 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03F 3/45219 Folded cascode stages

Abstract

A low voltage constant transconductance input stage is achieved with relatively simple design methodology. The approach uses current-mode techniques and is based upon the processing of signal currents, rather than handling the bias currents of input stages. Such an approach becomes universal and independent of the input stage transistor types (FET or bipolar) and their operating regions. Further, the arrangement considerably simplifies the design procedure of low voltage operational amplifiers. MOS and bipolar Op Amp input stages are described wherein almost constant g_m is achieved which is independent of the common mode input voltage ranging from rail-to-rail.

Claims

1. A method for operating an integrated circuit to enhance the consistency of transconductance exhibited by it, said circuit comprising a differential input stage having at least a first transistor pair of a first conductivity type providing a first output in response to an applied input signal and having at least a second transistor pair of a second conductivity type electrically coupled in parallel with said first transistor pair and responsive to said applied input to provide a second output, said method comprising the steps of:

simultaneously processing said first and second outputs with respect to the amplitudes exhibited thereby;

selecting that instantaneously occurring one of said first output or said second output exhibiting the highest amplitude to provide a selected output; and

applying said selected output corresponding with said highest amplitude, to a next stage of said integrated circuit.

2. The method of claim 1 in which:

said processing step monitors said first and second outputs with respect to their instantaneous current values; and

said selecting step is carried out continuously to provide said selected output as a current, exhibiting said highest amplitude.

3. The method of claim 1 in which said applying step inputs said applied output to a stage of an operational amplifier as said next stage.

4. The method of claim 2 in which:

said processing step carries out a D.C. term removal by subtraction of a first current component of said first output from a second current component of said first output which is opposite in phase from said first current component to derive a difference current, i_diff1, and carries out said D.C. term removal by subtraction of a third current component of said second output from a fourth component of said second output which is opposite in phase from said third current component to derive a difference current, i_diff2 ; and

said applying step provides said selected output, io as MAX (i_diff1, i_diff2).

5. The method of claim 1 in which:

said first transistor pair is of an n-conductivity type wherein said first output includes currents In1, In2, each having a D.C. term and a superimposed A.C. signal;

said second transistor pair is of a p-conductivity type wherein said second output includes currents, Ip1, Ip2 each having said D.C. term of the first transistor pair or another D.C term other than said first transistor pair D.C. term;

said differential input stage having a bias current, I_B applied thereto; and

said selecting step finds two currents, Io1 and Io2 which correspond respectively to MAX (In1, Ip1) and MAX (In2, Ip2), each exhibiting said A.C. signal combined with a max one of said D.C. terms.

6. The method of claim 5 wherein said selecting step includes the step of subtractively combining said currents Io1 and Io2 to remove said D.C. terms and providing said combined currents as said selected output.

7. The method of claim 1 in which:

said first transistor pair is of an n-conductivity type wherein said first output includes currents In1, In2, each having a D.C. term and a superimposed A.C. signal;

said second transistor pair is of a p-conductivity type wherein said second output includes currents Ip1, Ip2 each having said D.C. term of the first transistor pair or another D.C. term other than said first transistor pair D.C. term;

said differential input stage having a bias current, I_B applied thereto; and

said processing step initially carries out a subtraction of each said current, In1, In2, Ip1, Ip2 from said bias current, I_B to derive respective currents, In1'"'"', In2'"'"', Ip1'"'"', Ip2'"'"', then first and second output currents Io1, Io2, respectively, are determined as the minimums MIN(In1'"'"', Ip1'"'"'), MIN(In2'"'"', Ip2'"'"').

8. The method of claim 7 wherein said selecting step includes the step of subtractively combining said first and second output currents Io1 and Io2 to remove said D.C. terms and providing said combined currents as said selected output.

9. An integrated circuit, comprising:

a differential stage having at least an n-type transistor pair and at least a p-type transistor pair, said n-type and p-type transistor pairs being electrically coupled in parallel and responsive to an applied input to respectively provide corresponding first and second current outputs which are common mode voltage dependent; and

a selection circuit responsive to said current outputs and providing a selected current output corresponding with the first and second current output which exhibits a maximum current amplitude and maximum stage transconductance as an input to a next stage of said integrated circuit.

10. The integrated circuit of claim 9 in which said n-type and p-type transistor pairs are formed of composite transistors.

11. The integrated circuit of claim 9 in which:

said n-type transistor pair provides said first current output as two output currents In1 and In2 corresponding with said applied input and combined with a DC term;

said p-type transistor pair provides said second current output as two output currents Ip1 and Ip2 corresponding with said applied input combined with said or another DC term;

including a subtraction circuit responsive to derive difference currents I_diff1 and I_diff2 respectively as the subtractive combination of Ip1 with In2 and Ip1 with Ip2 exhibiting no DC term; and

said selection circuit provides said selected current output as that said difference current exhibiting maximum absolute amplitude.

12. The integrated circuit of claim 9 in which:

said differential stage comprises first and second n-type transistor pairs and third and fourth p-type transistor pairs, said n-type and p-type transistor pairs being electrically coupled in parallel and responsive to said applied input to provide said first current output as two current outputs, one from each of said first and second n-type transistor pairs and said second current output as two current outputs, one from each of said third and fourth p-type transistor pairs;

including a first subtraction circuit coupled to subtractively combine said two current outputs of said first n-type transistor pair to provide a difference current, i_n1 ;

including a second subtraction circuit coupled to subtractively combine said two current outputs of said second n-type transistor pair to provide a difference current, i_n2 ;

including a third subtraction circuit coupled to subtractively combine said two current outputs of said third p-type transistor pair to provide a difference current, i_p1 ;

including a fourth subtraction circuit coupled to subtractively combine said two current outputs of said fourth p-type transistor pair to provide a difference current, i_p2 ;

said selection circuit comprises;

a first Max-circuit responsive to said difference current i_n1 and to said difference current, i_p1 to select that difference current exhibiting maximum amplitude and having a max-output, i_o1 of given phase corresponding therewith;

a second Max-circuit responsive to said difference current, i_n2 and to said difference current, i_p2 to select that difference current exhibiting maximum amplitude and having a max-output, i_o2 corresponding therewith displaced in phase 180°

from said given phase, and

an output stage responsive to said max-output, i_ol and said max-output, i_o2, to subtractively combine them to provide said selected current output.

13. The integrated circuit of claim 12 in which each said first and second subtraction circuits comprises:

a two, branch p-type current mirror circuit having an intermediate output of given current direction; and

an auxiliary, two branch p-type branch current mirror circuit responsive to said intermediate output to provide said respective difference current.

14. The integrated circuit of claim 12 in which each said third and fourth subtraction circuits comprise a two branch n-type current mirror circuit.

15. The integrated circuit of claim 12 in which each said first and second Max-circuit comprises:

a first, three branch n-type, current mirror circuit, two branches of which are each responsive to a discrete one of said respective difference currents and one branch provides said max-output; and

a second, two branch n-type, current mirror circuit, one branch of which is coupled with that said first current mirror branch which provides said max-output and the other branch of which is coupled with one said first current mirror circuit branch which is responsive to a discrete one of said respective difference currents.

16. The integrated circuit of claim 9 in which:

said n-type transistor pair provides said first current output as two output currents In1 and In2 corresponding with said applied input and combined with a bias current derived DC term;

said p-type transistor pair provides said second current output as two output cents Ip1 and Ip2 corresponding with said applied input and combined with said or another bias current derived DC term;

said selection circuit comprises;

a first Max-circuit responsive to said output currents In1 and Ip1 of common phase relationship to select that output current exhibiting maximum amplitude and having a max-output, Io1 of given phase,

a second Max-circuit responsive to said output currents In2 and Ip2 of common phase relationship to select that output current exhibiting maximum amplitude and having a max-output, Io2 of phase opposite said given phase; and

an output stage responsive to said max-output Io1, and said max-output Io2, to subtractively combine them to remove said DC terms and derive said selected current output.

17. The integrated circuit of claim 16 in which said first Max-circuit includes:

a first current reversing circuit responsive to said output current In1 for deriving reversed In1 current;

a first, three branch n-type, current mirror circuit having a first branch responsive to said reversed In1 current, a second branch responsive to said output current Ip1 and a third branch deriving said max-output, Io1;

a second two branch n-type, current mirror circuit having a first branch coupled with said first current mirror circuit first branch and having a second branch coupled with said first current mirror circuit third branch.

18. The integrated circuit of claim 17 in which said second Max-circuit includes:

a second current reversing circuit responsive to said output current, In2 for deriving a reversed In2 current;

a third, three branch n-type, current minor circuit having a first branch responsive to said reversed In2 current, a second branch responsive to said output current, Ip2, and a third branch providing said max-output Io2 and

a fourth, two branch n-type current mirror circuit having a first branch coupled with said third current mirror circuit first branch and having a second branch coupled with said third current mirror circuit third branch.

19. The integrated circuit of claim 9 in which:

said differential stage n-type transistor pair provides said first current output as In1 and In2;

said p-type transistor pair provides said second current output as Ip1 and Ip2 and each said transistor pair having a bias current I_B applied thereto;

said selection circuit comprises;

a fast floating current mirror having two n-type branches and two p-type branches and responsive to said current outputs In2 and Ip1 to derive mirror outputs Ifcm2 and Ifcm4;

a second floating current minor having two n-type branches and two p-type branches and responsive to said current outputs In1 and Ip2 to derive mirror outputs Ifcm1 and Ifcm3,

wherein;

Ifcm1=Ifcm3=I_B -MAX(In1,Ip2) and

Ifcm2=Ifcm4=I_B -MAX(In2,Ip1) and

an output circuit responsive to said mirror outputs to provide said selected output in correspondence with the expression

io=Ifcm1-Ifcm2+Ifcm3-Ifcm4.

20. An integrated circuit, comprising:

a differential stage having an n-type transistor pair and a p-type transistor pair, said n-type and p-type transistor pairs having a bias current, I_B, applied thereto and being electrically coupled in parallel and responsive to an applied input to provide respective current outputs In1, In2, and Ip1, Ip2 corresponding with said applied input and combined with a DC term;

a processing circuit for subtracting said current outputs In1, In2, Ip1 and Ip2 from said bias current, I_B to provide respective subtracted currents In1'"'"', In2'"'"', Ip1'"'"' and Ip2'"'"' each exhibiting said or another DC term;

a first selector circuit responsive to said subtracted currents In1'"'"' and Ip1'"'"' for providing an initial output Io2 corresponding with a minimum amplitude of simultaneously occurring said subtracted currents In1'"'"' and Ip1'"'"'; and

a second selector circuit responsive to said subtracted currents In2'"'"' and Ip2'"'"' for providing an initial output Io1 corresponding with a minimum amplitude of simultaneously occurring said subtracted currents In2'"'"' and Ip2'"'"'.

21. The integrated circuit of claim 20 further comprising an output circuit responsive to subtractively combine said initial outputs Io1 and Io2 to provide a selected output, io exhibiting no DC term.

22. The integrated circuit of claim 20 in which said n-type and p-type transistor pairs are present as composite transistor pairs.

23. The integrated circuit of claim 20 in which:

said selector circuit comprises a current mode minimum amplitude selecting circuit including a first, three-branch p-type current mirror circuit having a first branch responsive to said subtracted current Ip1'"'"', a second branch, and a third branch in electrical connection with said initial output Io2,

a second n-type two-branch current mirror circuit having a first branch responsive to said subtracted current In1'"'"' and a second branch coupled with said first current mirror circuit second branch, and

a third n-type two-branch current mirror circuit having a first branch coupled with said second of said first and second current mirror circuits,and having a second branch coupled with said first current mirror third branch.

24. The integrated circuit of claim 21 in which said output circuit comprises a p-type two-branch current mirror circuit having a first branch coupled to said initial output Io1 and said bias current I_B and a second branch coupled with said initial output Io2 and said bias current I_B and deriving said selected output.