Apparatus for forming input data for a logic simulator

• US 5,715,170 A
• Filed: 04/19/1995
• Issued: 02/03/1998
• Est. Priority Date: 04/20/1994
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Nakamori, Tutomu
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/424,624
• Time in Patent Office: 1,021 Days
• Field of Search: 364/488, 364/489, 364/578, 364/490
• US Class Current: 703/19
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

An apparatus for forming input data for a logic simulator executes the operation processing so as to convert a net list using elements as bases into a net list using cell units as bases, and feeds the net list to a logic simulator. The apparatus for forming input data for a logic simulator is constituted by a processing device which, for a net list which uses elements as units and is constituted by connection data among the elements including parasitic resistances and parasitic capacitances, feeds, to a logic simulator, the data related to nets, parasitic resistances and parasitic capacitances but excluding those nets, and parasitic resistances and parasitic capacitances that are completed in a cell.

Claims

1. An apparatus for forming input data for a logic simulator which simulates and verifies timing in a semiconductor integrated circuit, said apparatus comprising:

memory means for storing a net list comprising connection data among circuit elements of a semiconductor device, said connection data including parasitic resistances and parasitic capacitances;

processing means connected to said memory means for processing said net list as a plurality of cells, said processing means excluding parasitic resistances and parasitic capacitances which are completed in a cell of said plurality of cells, said processing means outputting data from said net list related to nets, parasitic resistances, and parasitic capacitances which are not excluded from the net list, thereby forming input data for a logic simulator at the logic cell level.

2. An apparatus according to claim 1, said apparatus further comprising:

layout data-holding means connected to said memory means for holding data regarding the circuit elements of the semiconductor integrated circuit as units;

basic net list data-holding means connected to said memory means for holding basic net list data;

net list-forming means connected to said processing means for forming the net list comprising the connection data among the circuit elements of the semiconductor device, based upon the data stored in the layout data-holding means and the basic net list data-holding means;

wherein said processing means removes nets, parasitic resistances, and parasitic capacitances that are completed in said cell, and forms data relative to other nets, parasitic resistances, and parasitic capacitances for net lists formed by the net list-forming means; and

feeding means coupled to said processing means for feeding data output from the processing means to the logic simulator.

3. An apparatus as recited in claim 2, wherein said processing means comprises excluding means for excluding the parasitic resistances and parasitic capacitances, and for excluding nets, which are completed in the cell in the plurality of cells, said processing means also calculating a delay time of wiring for the cell based upon other nets, parasitic resistances, and capacitances.

4. An apparatus as recited in claim 3, wherein said feeding means feeds data representing the delay time in each of the cells based upon output from the processing means, to the logic simulator.

5. An apparatus according to any of claims 1 to 4, wherein said excluding means excludes parasitic resistance and extracts only data related to other nets, other parasitic resistances, and other parasitic capacitances when a net connected to a cell is represented by a symbol in the net list is divided into two or more nodes by the parasitic resistance associated therewith.

6. An apparatus according to any of claims 1 to 4, wherein when a net connected to a terminal of the cell represented by a symbol in the basic net list is divided into at least two nodes by the parasitic resistance, and wherein the cell serves as a passing cell for other nets, said processing means excludes the parasitic resistance when a delay time in the passing cell is calculated, and wherein the processing means includes the parasitic resistance when a delay time in the net connected to the terminal is to be calculated.

7. An apparatus according to any of claims 1 to 4, wherein the processing means compares the parasitic resistances and the parasitic capacitances in the net list with the parasitic resistances and parasitic capacitance of a cell that has been stored in the basic net list data-holding means, to determine whether the parasitic resistances and parasitic capacitances are within or without said cell, said processing means excluding the parasitic resistances and parasitic capacitances when they exist within the cell.

8. An apparatus according to any of claims 1 to 4, wherein the processing means includes allowable data-holding means, and wherein the processing means compares allowable resistances and allowable capacitances in each of a plurality of cells stored in the allowable data-holding means with each other, so that processing means outputting alarm data for parasitic resistances and parasitic capacitances which exceed said allowable resistances and allowable capacitances.

9. An apparatus according to any of claims 1 to 4, wherein said processing means divides data corresponding to the elements of the semiconductor device arranged in the net list into the plurality of cells, said processing means temporarily deleting the parasitic resistances of terminals connected to predetermined elements of the semiconductor device in a group, and for temporarily deleting parasitic capacitances of terminals of the predetermined elements which are not grounded, and wherein said processing means calculates delay time of wiring of the group based upon remaining nets, parasitic resistances, and parasitic capacitances, said processing means also returning the temporarily deleted parasitic resistances and capacitances to initial positions and repeating the temporary deletion of the parasitic capacitances and parasitic resistances and repeating the calculation of delay times for other predetermined groups of elements, said processing means halting operation after processing has been executed for all of the cells of the plurality of cells.

10. An apparatus according to claim 9, wherein said feeding means feeds delay time data for each of the plurality of cells to the logic simulator.

11. An apparatus according to claim 9, wherein the feeding means first feeds the net list data formed by the net list-forming means to the logic simulator, and when said feeding means then feeds delay time data for each of the cells to the logic simulator.

12. An apparatus according to claim 2, wherein said processing means comprises a first storage means for receiving and storing data from the net list data formed by the net list-forming means, operation means for reading the net list data from the first storage means, said operation means also deleting nets, parasitic resistances, and parasitic capacitances which are completed in a cell but are not used for calculation of the delay times of the cells, said operation means also calculating a delay time of a predetermined cell based upon data related to other nets, parasitic resistances, and parasitic capacitances, said processing means also comprising second storage means for temporarily storing delay time data for each of the plurality of cells calculated by the operation means, said second storage means being connected to said feeding means.

13. A method for forming input data for a logic simulator, said method comprising the steps of:

preparing a net list based upon data representing elements of a semiconductor device and connection data among the elements including parasitic resistances and parasitic capacitances;

dividing data of the net list into cell-groups having predetermined units of cells, each cell being based upon at least one element of the semiconductor device and corresponding connection data;

determining whether a predetermined cell has any nets, parasitic resistances, and parasitic capacitances completed therein;

excluding the presence of any nets, parasitic resistances and parasitic capacitances which are determined in the determining step to be completed in the cell;

calculating a delay time of the cell based upon data related to other nets, parasitic resistances, and parasitic capacitances;

repeating said determining step and said excluding step for each cell of the plurality of cells in the net list;

feeding the delay time data of the cells to the logic simulator after completion of calculation of the delay time for all of the plurality of cells.