Method for automatic clock qualifier selection in reprogrammable hardware emulation systems

• US 5,715,172 A
• Filed: 04/26/1996
• Issued: 02/03/1998
• Est. Priority Date: 08/26/1994
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Tzeng, Ping-San
• Primary Examiner(s): LOUIS JACQUES, JACQUES H
• Application Number:
  US08/638,309
• Time in Patent Office: 648 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 364/580, 371/22.2, 371/22.1, 371/22.4, 371/22.6, 371/22.3, 371/25.1, 371/22.5, 326/40-43, 326/93, 326/95, 326/38, 326/46-50, 326/39, 326/36, 326/44, 395/500, 395/551-556, 395/183.13, 395/183.09, 395/183.01, 395/183.04, 395/183.1, 395/183.17, 327/203, 327/210-218, 327/141, 327/198-199
• US Class Current: 716/103
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level

Abstract

A method of identifying potential clock qualifiers in netlist description of an integrated circuit, the netlist comprising logic elements. The method comprises the steps of initializing every net of the netlist to a speed of zero, identifying all potential clock nets so that all signals with a path to a clock source has a speed of one, computing the maximum speed of each output net of each of the logic elements in the netlist, and marking as a potential clock qualifier any net of the netlist that is input to the logic elements in the netlist that is slower than the maximum speed of any net that is input to the logic elements.

Claims

1. A method of identifying potential clock qualifier nets in a netlist description of an integrated circuit prior to implementation in a reprogrammable logic emulation system, said netlist including nets which can be specified by the user as clock source nets, said netlist further including login elements with input nets and output nets, said logic elements including combinational logic elements, sequential logic elements with feedback and sequential logic elements without feedback, said input nets of said sequential logic elements with feedback comprising data input nets and clock input nets and said input nets of said sequential logic elements without feedback comprising data input nets and clock input nets, said method comprising:

initializing every net of said netlist to a speed of "zero";

identifying all potential clock nets by assigning a speed of "one" to all nets with a path to said clock source nets, irrespective of the delay of said potential clock nets;

computing the maximum speed of each of said output nets of each of said logic elements in said netlist, irrespective of the delay of each of said output nets; and

marking all of said input nets for a given logic element in said netlist which have a speed less than the highest speed of any input net for that given logic element as one of said potential clock qualifier nets, said computing step comprising the steps of;

setting all said output nets from said combinational logic elements to the highest speed of any of said input nets to said combinational logic elements, irrespective of the delay of said output nets from said combinational logic elements;

setting all said output nets from said sequential logic elements without feedback to either the speed of said data input nets to said sequential logic elements without feedback or to one-half the speed of said clock input nets on said sequential logic elements without feedback, whichever is less, irrespective of the delay of said output nets from said sequential elements without feedback; and

setting all of said output nets from said sequential logic elements with feedback to a speed of one-half the speed of said clock input nets on said sequential logic elements with feedback, irrespective of the delay of said output nets from said sequential logic elements with feedback.

2. A method of identifying potential clock qualifier nets in a netlist description of an integrated circuit prior to implementation into a reprogrammable logic emulation system, said netlist description having nets which can be specified by the user as clock source nets, said netlist description further comprising clock nets and logic elements, said logic elements including combinational logic elements having input nets and output nets, sequential logic elements without feedback having clock input nets, data input nets and output nets, and sequential logic elements with feedback having clock input nets, data input nets and output nets, said method comprising:

setting every net of said netlist to a speed of zero, irrespective of the delay of said net;

changing all of said user-specified clock source nets to a speed of one, irrespective of the delay of said user-specified clock source nets;

changing all of said output nets from each of said logic elements to a speed of one whenever one of said input nets to that logic element has a speed of one, irrespective of the delay of said output nets from each of said logic elements;

calculating a maximum speed of each of said output nets of each logic element by;

(a) changing all said output nets from said combinational logic elements to the speed equal to the highest speed of any of said input nets, irrespective of the delay of said output nets from said combinational logic elements;

(b) changing all said output nets from said sequential logic elements without feedback to the speed of either said data input net speed of said sequential logic elements without feedback or one-half the clock input net speed, whichever is less, irrespective of the delay of said output nets from said sequential logic elements without feedback;

(c) changing all said output nets from said sequential logic elements with feedback to the speed of one-half the clock input net speed, irrespective of the delay of said output nets from said sequential logic elements with feedback; and

marking any input net to said logic elements that has a speed less than the highest speed of any of said input net to said logic elements as one of said potential clock qualifier nets.