Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks

• US 5,715,193 A
• Filed: 05/23/1996
• Issued: 02/03/1998
• Est. Priority Date: 05/23/1996
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Quantum Devices Inc (Micron Technology, Inc.)
• Inventors: Norman, Robert
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/652,779
• Time in Patent Office: 621 Days
• Field of Search: 365/185.02, 365/185.11, 365/185.29, 365/185.33, 365/185.09
• US Class Current: 365/185.02
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A memory circuit including at least one of flash memory calls organized into one or more physically separate decode blocks and a controller which monitors the disturb effect on each independently erasable "erase" block of cells of each decode block due to erasures of other erase blocks in the same decode block, and a method of operating such a circuit. Preferably, the controller controls memory operations of each array in addition to monitoring the disturb effect on each erase block. The disturb effect causes cells of an erase block to lose charge from their floating gates each time an erase operation is performed on another erase block in the same decode block. Preferably, each time an erase block is erased, the controller updates a table for the decode block which contains the erased block by adding a unit of disturb to the count for each other erase block in the decode block and resetting the count for the erased block to zero. Also preferably, the controller performs a refresh operation on each erase block whose disturb count reaches a predetermined maximum value. During the refresh operation, any necessary recovery procedures are performed to restore the proper charge to the floating gate of each cell of the erase block, thus preventing any erroneous reads of data that would otherwise occur (due to the disturb effect) absent performance of the refresh operation.

Claims

1. A flash memory circuit, including:

a flash memory array comprising at least a first decode block of flash memory cells, wherein the first decode block includes at least two erase blocks of the cells, each of the erase blocks is independently erasable and includes at least one row of said cells, and each of the erase blocks is subject to a disturb effect due to each erasure of another of the erase blocks in the first decode block; and

disturb count circuitry which generates count signals indicative of a disturb count for each of the erase blocks of the first decode block and which generates from the count signals a set of updated count signals in response to each erasure of at least one of the erase blocks of the first decode block, where each said disturb count is indicative of the disturb effect on a different one of the erase blocks.

2. The circuit of claim 1, wherein each of the count signals is indicative of a disturb unit count for a different one of the erase blocks, and the updated count signals generated in response to erasure of a first one of the erase blocks of the first decode block include a decreased count signal indicative of a decreased disturb unit count for said first one of the erase blocks and an increased count signal for each other one of the erase blocks, where each said increased count signal is indicative of an increased disturb unit count for said each other one of the erase blocks.

3. The circuit of claim 2, wherein the decreased count signal is indicative of a disturb unit count of zero for said first one of the erase blocks.

4. The circuit of claim 2, also including a controller which controls memory operations of the flash memory array including each said erasure of at least one of the erase blocks, wherein the controller includes the disturb count circuitry, and wherein the controller is programmed with software so that said controller performs a refresh operation on each of the erase blocks whose disturb unit count reaches a predetermined maximum value.

5. The circuit of claim 4, wherein the refresh operation includes a final step of generating an updated count signal, indicative of an intermediate disturb count value, for said each of the erase blocks whose disturb unit count reaches a predetermined maximum value, wherein said intermediate disturb count value is less than said predetermined maximum value.

6. The circuit of claim 5, wherein the intermediate disturb count value is equal to one half of said predetermined maximum value.

7. The circuit of claim 5, wherein the refresh operation includes:

a step of identifying at least one disturbed cell of said each of the erase blocks whose disturb unit count reaches a predetermined maximum value, where each said disturbed cell has a floating gate which has lost at least a minimum amount of charge due to the disturb effect; and

a step of reprogramming each said disturbed cell.

8. The circuit of claim 7, wherein the step of reprogramming each said disturbed cell restores the floating gate of said each disturbed cell to an undisturbed charge level.

9. The circuit of claim 1, also including:

a memory, connected to the disturb count circuitry, which receives and stores each said set of updated count signals.

10. The circuit of claim 1, wherein the flash memory array also includes a second decode block of the flash memory cells, said second decode block includes at least two erase blocks of the cells, each of the erase blocks in the second decode block is subject to a disturb effect due to each erasure of another of the erase blocks in said second decode block, wherein the circuit also includes:

a controller which controls memory operations of the flash memory array including each said erasure of at least one of the erase blocks in a selected decode block, wherein the selected decode block is a selected one of the first decode block and the second decode block, wherein the controller is programmed with software so that said controller controls generation of count signals indicative of a disturb count for each of the erase blocks of the selected decode block and processes the count signals to generate a set of updated count signals in response to each said erasure of at least one of the erase blocks of said selected decode block.

11. A flash memory circuit, including:

a flash memory array comprising at least a first decode block of flash memory cells, wherein the first decode block includes at least two erase blocks of the cells, each of the erase blocks is independently erasable and includes at least one row of said cells, and each of the erase blocks is subject to a disturb effect due to each erasure of another of the erase blocks in the first decode block;

a second flash memory array comprising at least a second decode block of flash memory cells, wherein the second decode block includes at least two erase blocks of the cells, each of the erase blocks is independently erasable and includes at least one row of said cells, and each of the erase blocks is subject to a disturb effect due to each erasure of another of the erase blocks in the second decode block; and

a controller which controls memory operations of the flash memory array and the second flash memory array including an erasure of any selected one of the erase blocks in a selected decode block, wherein the selected decode block is a selected one of the first decode block and the second decode block, wherein the controller is programmed with software so that said control generates count signals indicative of a disturb count for each of the erase blocks of the selected decode block and processes the count signals to generate a set of updated count signals in response to each erasure of at least one of the erase blocks of said selected decode block.

12. The circuit of claim 11, wherein each of the count signals is indicative of a disturb unit count for a different one of the erase blocks of the selected decode block, and the updated count signals generated in response to erasure of a first one of the erase blocks of said selected disturb block include a decreased count signal indicative of a decreased disturb unit count for said first one of the erase blocks and an increased count signal for each other one of the erase blocks of the selected decode block, where each said increased count signal is indicative of an increased disturb unit count for said each other one of the erase blocks of the selected decode block.

13. The circuit of claim 12, wherein the decreased count signal is indicative of a disturb unit count of zero for said first one of the erase blocks.

14. The circuit of claim 11, wherein the controller is also programmed with software so that said controller performs a refresh operation on each of the erase blocks whose disturb unit count reaches a predetermined maximum value.

15. The circuit of claim 14, wherein the refresh operation includes a final step of generating an updated count signal, indicative of an intermediate disturb count value, for said each of the erase blocks whose disturb unit count reaches a predetermined maximum value, wherein said intermediate disturb count value is less than said predetermined maximum value.

16. A flash memory circuit, including:

a flash memory array comprising at least one decode block of flash memory cells, wherein each said decode block includes at least two erase blocks of the cells, each of the erase blocks is independently erasable and includes at least one row of said cells, and each of the erase blocks is subject to a disturb effect due to each erasure of another of the erase blocks in the decode block containing said each of the erase blocks;

a disturb count memory which stores a disturb count table for each said decode block, said disturb count table comprising data indicative of a disturb unit count for each of the erase blocks, where each said disturb unit count is indicative of the disturb effect on a different one of the erase blocks; and

circuitry which generates the disturb count table and stores said disturb count table in the disturb count memory.

17. The circuit of claim 16, also including:

a controller which controls memory operations of the flash memory array including erasure of any selected one of the erase blocks in a selected decode block, wherein the selected decode block is a selected one of said at least one decode block, where the controller is programmed with software which controls generation of count signals indicative of a disturb unit count for each of the erase blocks of the selected decode block, and which processes the count signals to generate a set of updated count signals in response to each erasure of at least one of the erase blocks of said selected decode block, generates said disturb count table from the set of updated count signals, and controls storage of the disturb count table in the disturb count memory in response to said each erasure of at least one of the erase blocks of said selected decode block.

18. The circuit of claim 17, wherein each of the count signals is indicative of a disturb unit count for a different one of the erase blocks of the selected decode block, and the updated count signals generated in response to erasure of a first one of the erase blocks of said selected disturb block include a decreased count signal indicative of a decreased disturb unit count for said first one of the erase blocks and an increased count signal for each other one of the erase blocks of the selected decode block, where each said increased count signal is indicative of an increased disturb unit count for said each other one of the erase blocks of the selected decode block.

19. A flash memory circuit, including:

a flash memory array comprising at least a first decode block of flash memory cells, wherein the first decode block includes at least two erase blocks of the cells, each of the erase blocks is independently erasable and includes at least one row of said cells, and each of the erase blocks is subject to a disturb effect due to each erasure of another of the erase blocks in the first decode block; and

a controller which controls memory operations of the flash memory array including erasure of at least one of the erase blocks, wherein the controller is programmed with software so that the controller generates count signals indicative of a disturb count for each of the erase blocks of the first disturb block and generates from the count signals a set of updated count signals in response to each erasure of at least one of the erase blocks of the first disturb block, where each said disturb count is indicative of the disturb effect on a different one of the erase blocks, and wherein the controller is also programmed with software so that said controller performs a refresh operation on each of the erase blocks whose disturb unit count reaches a predetermined maximum value,

where the refresh operation includes a step of identifying at least one disturbed cell of said each of the erase blocks whose disturb unit count reaches a predetermined maximum value, where each said disturbed cell has a floating gate which has lost at least a minimum amount of charge due to the disturb effect, and a step of reprogramming each said disturbed cell.

20. The circuit of claim 19, wherein the step of reprogramming each said disturbed cell restores the floating gate of said each disturbed cell to an undisturbed charge level.

21. The circuit of claim 19, wherein at least some of the cells of the first decode block store error correction code bits, and wherein the step of identifying at least one disturbed cell includes the steps of:

(a) reading cells of said each of the erase blocks whose disturb unit count reaches a predetermined maximum value, including cells which store at least a subset of the error correction code bits; and

(b) processing the error correction code bits read during step (a) to identify said at least one disturbed cell.

22. A method for monitoring disturb status of erase blocks of a flash memory array, where the array comprises at least one decode block of flash memory cells, each said decode block includes at least two erase blocks of the cells, each of the erase blocks is independently erasable and includes at least one row of said cells, and each of the erase blocks is subject to a disturb effect due to each erasure of another of the erase blocks in the decode block containing said each of the erase blocks, said method including the steps of:

(a) generating and storing a disturb count table for each said decode block, said disturb count table comprising data indicative of a disturb unit count for each of the erase blocks, where each said disturb unit count is indicative of the disturb effect on a different one of the erase blocks; and

(b) generating and storing an updated disturb count table in response to each erasure of at least one of the erase blocks of a first decode block of the array, wherein the updated disturb count table includes data indicative of a decreased disturb unit count signal for said at least one of the erase blocks and data indicative of an increased disturb unit count signal for each other one of the erase blocks of the first decode block.

23. The method of claim 22, also including the step of:

(c) performing a refresh operation on each of the erase blocks whose disturb unit count reaches a predetermined maximum value.

24. The method of claim 23, wherein step (c) includes a final step of:

generating and storing as part of the disturb count table, an intermediate disturb unit count value for said each of the ease blocks whose disturb unit count reaches a predetermined maximum value, where said intermediate disturb count value is less than said predetermined maximum value.

25. The method of claim 24, wherein the intermediate disturb count value is equal to one half of said predetermined maximum value.

26. The method of claim 23, wherein step (c) includes the steps of:

(d) identifying at least one disturbed cell of said each of the erase blocks whose disturb unit count reaches a predetermined maximum value, where each said disturbed cell has a floating gate which has lost at least a minimum amount of charge due to the disturb effect; and

(e) reprogramming each said disturbed cell.

27. The method of claim 26, wherein step (c) includes the step of:

(f) after step (e), generating, and storing as part of the disturb count table, an intermediate disturb unit count value for said each of the erase blocks whose disturb unit count reaches a predetermined maximum value, where said intermediate disturb count value is less than said predetermined maximum value.

28. The method of claim 26, wherein step (e) includes the step of:

restoring the floating gate of each said disturbed cell to an undisturbed charge level.

29. The method of claim 23, wherein step (c) includes the steps of:

designating, as an obsolete storage location, a subset of the cells of said each of the erase blocks; and

processing the updated disturb count table to designate, as a substitute location for the obsolete storage location, another subset of the cells of the flash memory array.

30. A method for monitoring disturb status of erase blocks of a flash memory array, where the array comprises at least a first decode block of flash memory cells, said first decode block includes at least two erase blocks of the cells, each of the erase blocks is independently erasable and includes at least one row of said cells, and each of the erase blocks is subject to a disturb effect due to each erasure of another of the erase blocks in the first decode block, said method including the steps of:

(a) generating count signals indicative of a disturb count for each of the erase blocks of the first disturb block, where each said disturb count is indicative of the disturb effect on a different one of the erase blocks;

(b) generating from the count signals a set of updated count signals in response to each erasure of at least one of the erase blocks of the first disturb block; and

(c) performing a refresh operation on each of the erase blocks whose disturb unit count reaches a predetermined maximum value.

31. The method of claim 30, wherein step (c) includes the steps of:

(d) identifying at least one disturbed cell of said each of the erase blocks whose disturb unit count reaches a predetermined maximum value, where each said disturbed cell has a floating gate which has lost at least a minimum amount of charge due to the disturb effect; and

(e) reprogramming each said disturbed cell.

32. The method of claim 31, wherein step (e) includes the steps of:

restores the floating gate of each said disturbed cell to an undisturbed charge level.

33. The method of claim 32, wherein at least some of the cells of the first decode block store error correction code bits, and wherein step (d) includes the steps of:

(f) reading cells of said each of the erase blocks whose disturb unit count reaches a predetermined maximum value, including cells which store at least a subset of the error correction code bits; and

(g) processing the error correction code bits read during step (f) to identify said at least one disturbed cell.

34. The method of claim 30, wherein step (c) includes the steps of:

processing the count signals to designate, as an obsolete storage location, a subset of the cells of said each of the erase blocks; and

processing the count signals to designate, as a substitute location for the obsolete storage location, another subset of the cells of the flash memory array.