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Autonomous high speed linear space address mode translation for use with a computer hard disc system

  • US 5,715,418 A
  • Filed: 07/27/1994
  • Issued: 02/03/1998
  • Est. Priority Date: 07/27/1994
  • Status: Expired due to Fees
First Claim
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1. A translator unit for autonomously translating between linear address spaces, wherein said address spaces are associated with a hard disc storage unit, addressable in terms of cylinder, head, and sector numbers, or a sequential logical block address is used to store data for use by a host central processor unit (CPU), comprising:

  • a decoder for decoding bits present in commands issued by said host computer CPU, wherein different combinations of decoded said bits are associated with different modes of address translation;

    an algorithmic function generator for providing a set of real-time translation functions including at least (a) logical block address to logical cylinder-head-sector address mode conversion, and (b) physical cylinder-head-sector address to physical block address mode conversion;

    a mode selector, coupled to send algorithmic function generator, for selecting a chosen one from said set of translation functions in response to the decoded said bits;

    wherein said algorithmic function generator translates address space associated with said commands in response to the decoded said bits;

    said generator using an equation given by;

    
    
    space="preserve" listing-type="equation">X/Y=t0+r0
    
    
    space="preserve" listing-type="equation">t0/Z=t1+r1
    
    
    space="preserve" listing-type="equation">t1+W=r2where X is said block address, Y is a physical sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone.

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