Autonomous high speed linear space address mode translation for use with a computer hard disc system

• US 5,715,418 A
• Filed: 07/27/1994
• Issued: 02/03/1998
• Est. Priority Date: 07/27/1994
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology plc (Seagate Technology Holdings Plc)
• Inventors: Virjee, Pervez E., Lum, Marvin Mang-Yin, Atsatt, Sean R., Masiewicz, John Chester
• Primary Examiner(s): Moore, David K.
• Assistant Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US08/281,445
• Time in Patent Office: 1,287 Days
• Field of Search: 395/412, 395/413, 395/404, 395/416, 395/419, 395/182.05, 395/440, 395/441, 369/32
• US Class Current: 711/202
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0676 Magnetic disk device

Abstract

Translating between physical and logical (or virtual) address spaces occurs autonomously using information decoded by an address mode translator from command bits within a host CPU issued command. The translator communicates with a hard disc controller unit local microprocessor or microcontroller and controller unit task registers. A host CPU issued command interrupts the local microprocessor and activates the address mode translator by writing to an appropriate controller unit task register using indirect addressing. The address mode translator preferably provides four algorithms, with algorithm selection occurring autonomously according to the decoded command bits. The algorithms provide physical block address to physical CHS cylinder-head-sector conversion, logical CHS to logical block address conversion, and also provide divide and multiply functions, useful for disc caching. Upon completion of the conversion or other function procedure, the address translator signals that the processed result is ready for reading by the controller unit local microprocessor or microcontroller. The translator may be implemented as a microprogrammed sequencer with an instruction set tailored to perform linear address translations and stored in memory associated with the local microprocessor. Alternatively, the instruction set may be downloaded by the microprocessor from disc drive software. The address translator provides the microprocessor with a translated address in a usable form more rapidly than if the local microprocessor had made the translation.

Claims

1. A translator unit for autonomously translating between linear address spaces, wherein said address spaces are associated with a hard disc storage unit, addressable in terms of cylinder, head, and sector numbers, or a sequential logical block address is used to store data for use by a host central processor unit (CPU), comprising:

a decoder for decoding bits present in commands issued by said host computer CPU, wherein different combinations of decoded said bits are associated with different modes of address translation;

an algorithmic function generator for providing a set of real-time translation functions including at least (a) logical block address to logical cylinder-head-sector address mode conversion, and (b) physical cylinder-head-sector address to physical block address mode conversion;

a mode selector, coupled to send algorithmic function generator, for selecting a chosen one from said set of translation functions in response to the decoded said bits;

wherein said algorithmic function generator translates address space associated with said commands in response to the decoded said bits;

said generator using an equation given by;

space="preserve" listing-type="equation">X/Y=t0+r0

space="preserve" listing-type="equation">t0/Z=t1+r1

space="preserve" listing-type="equation">t1+W=r2

where X is said block address, Y is a physical sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone.

2. The translator unit of claim 1, wherein said address spaces are associated with a hard disc controller unit buffer.

3. The translator unit of claim 1, wherein said algorithmic function means translates said address space using hardware selected from the group consisting of (a) a state machine, (b) a microcontroller, and (c) a local microprocessor associated with said translator unit.

4. The translator unit of claim 1, wherein said algorithmic function means further provides at least one additional function selected from the group consisting of (c) division, and (d) multiplication.

5. A translator unit for autonomously translating between linear address spaces, wherein said address spaces are associated with a hard disc storage unit, addressable in terms of cylinder, head and sector numbers, or a sequential logical block address used to store data for use by a host central processor unit (CPU), comprising:

a decoder for decoding bits present in commands issued by said host computer CPU, wherein different combinations of decoded said bits are associated with different modes of address translation;

an algorithmic function generator for providing a set of real-time translation functions including at least (a) logical block address to logical cylinder-head-sector address mode conversion, and (b) physical cylinder-head-sector address to physical block address mode conversion;

a mode selector coupled to said algorithmic function generator, for selecting a chosen one from said set of translation functions in response to the decoded said bits;

wherein said algorithmic function generator translates address space associated with said commands in response to the decoded said bits;

said generator using an equation given by;

space="preserve" listing-type="equation">X/Y=t0+r0

space="preserve" listing-type="equation">t0/Z=t1+r1

space="preserve" listing-type="equation">t1+W=r2

where X is said block address, Y is a physical sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone;

said algorithmic function generator translating a cylinder-head-sector address to a block address using an equation given by;

space="preserve" listing-type="equation">block address=((((C*Nh)+H)*Ns)+S-1)

where C is a head number, Nh is a head and drive number, H is a head number, Ns is a sector and track number, and S is a sector number.

6. A translator unit for autonomously translating between linear address spaces wherein said address spaces are associated with a hard disc storage unit addressable in terms of cylinder, head, and sector numbers, or a sequential logical block address used to store data for use by a host central processor unit (CPU), comprising:

a decoder for decoding bits present in commands issued by said host computer CPU, wherein different combinations of decoded said bits are associated with different modes of address translation;

an algorithmic function generator for providing a set of real-time translation functions including at least (a) logical block address to logical cylinder-head-sector address mode conversion, and (b) physical cylinder-head-sector address to physical block address mode conversion;

a mode selector, coupled to said algorithmic function generator for selecting a chosen one from said set of translation functions in response to the decoded said bits;

wherein said algorithmic function generator translates address space associated with said commands in response to the decoded said bits;

said generator using an equation given by;

space="preserve" listing-type="equation">X/Y=t0+r0

space="preserve" listing-type="equation">t0/Z=t1+r1

space="preserve" listing-type="equation">t1+W=r2

where X is said block address, Y is a physical sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone;

means for testing whether the host CPU has written a command;

a DONE register for testing whether said translator unit is presently available for translation;

means for branching, in response to an output from said means for decoding, to a portion of said algorithmic function generator providing a real-time translation function corresponding to an output of said decoder;

means for confirming that a host CPU command has been received, and if affirmative, means for reading task registers associated with said host CPU;

wherein if said decoder determines that a multiplication function is required, said algorithmic function generator provides a multiplication function;

wherein if said decoder determines that a division function is required, said algorithmic function generator provides a division function;

wherein if said decoder determines that a said block address is to be converted to a cylinder-head-sector address said algorithmic function generator uses an equation given by;

space="preserve" listing-type="equation">X/Y=t0+r0

space="preserve" listing-type="equation">t0/Z=t1+r1

space="preserve" listing-type="equation">t1+W=r2

where X is said block address, Y is a sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone;

wherein if said decoder determines that a said cylinder-head-sector address is to be converted to a block address, said translator unit confirms receipt of said host CPU command and reads said task registers associated with said host CPU, and converts said address using an equation given by;

space="preserve" listing-type="equation">block address=((((C*Nh)+H)*Ns)+S-1)

where C is a head number, Nh is a head and drive number, H is a head number, Ns is a sector and track number, and S is a sector number; and

means for setting said DONE register means upon translation completion.

7. A method for autonomously translating between linear address spaces wherein said address spaces are associated with a hard disc storage unit, addressable in terms of cylinder, head, and sector numbers, used to store data for use by a host central processor unit (CPU), the method comprising the following steps:

decoding bits present in commands issued by said host computer CPU, wherein different combinations of decoded said bits are associated with different modes of address translation;

providing a set of real-time translation functions including at least (a) logical block address to logical cylinder-head-sector address mode conversion, and (b) physical cylinder-head-sector address to physical block address mode conversion;

selecting, in response to decoded said bits, a chosen one from said set of translation functions;

wherein said algorithmic function means translates address space associated with said commands in response to the decoded said bits;

wherein the step of providing translates a block address to a cylinder-head-sector address using an equation given by;

space="preserve" listing-type="equation">X/Y=t0+r0

space="preserve" listing-type="equation">t0/Z=t1+r1

space="preserve" listing-type="equation">t1+W=r2

where X is said block address, Y is at sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone.

8. The method of claim 7 wherein said address spaces are associated with a hard disc controller unit buffer.

9. The method of claim 7, wherein the step of providing translates said address space using hardware selected from a group consisting of (a) a state machine, (b) a microcontroller, and (c) a local microprocessor associated with said translator unit.

10. The method of claim 7, wherein the step of providing further provides at least one additional function selected from a group consisting of (c) division, and (d) multiplication.

11. A method for autonomously translating between linear address spaces wherein said address spaces are associated with a hard disc storage unit addressable in terms of cylinder, head, and sector numbers, used to store data for use by a host central processor unit (CPU) the method comprising the following steps:

decoding bits present in commands issued by said host computer CPU wherein different combinations of decoded said bits are associated with different modes of address translation;

providing a set of real-time translation functions including at least (a) logical block address to logical cylinder-heed-sector address mode conversion and (b) physical cylinder-head-sector address to physical block address mode conversion;

selecting, in response to decoded said bits, a chosen one from said set of translation functions;

wherein said algorithmic function means translates address space associated with said commands in response to the decoded said bits;

wherein the step of providing translates a block address to a cylinder-head-sector address using an equation given by;

space="preserve" listing-type="equation">X/Y=t0+r0

space="preserve" listing-type="equation">t0/Z=t1+r1

space="preserve" listing-type="equation">t1+W=r2

where X is said block address Y is a sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone;

wherein the step of providing translates a cylinder-head-sector address to a block address using an equation given by;

space="preserve" listing-type="equation">block address=((((C*Nh)+H)*Ns)+S-1)

where C is a head number, Nh is a head and drive number, H is a head number, Ns is a sector and track number, and S is a sector number.

12. A method for autonomously translating between linear address spaces wherein said address spaces are associated with a hard disc storage unit addressable in terms of cylinder, head, and sector numbers used to store data for use by a host central processor unit (CPU), the method comprising the following steps:

decoding bits present in commends issued by said host computer CPU, wherein different combinations of decoded said bits are associated with different modes of address translation;

providing a set of real-time translation fractions including at least (a) logical block address to logical cylinder-head-sector address mode conversion, and (b) physical cylinder-head-sector address to physical block address mode conversion;

selecting in response to decoded said bits, a chosen one from said set of translation functions;

wherein said algorithmic function means translates address space associated with said commands in response to the decoded said bits;

wherein the step of providing translates a block address to a cylinder-head-sector address using an equation given by;

space="preserve" listing-type="equation">X/Y=t0+r0

space="preserve" listing-type="equation">t0/Z=t1+r1

space="preserve" listing-type="equation">t1+W=r2

where X is said block address, Y is a sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone;

including additional steps of;

testing whether the host CPU has written a command;

providing DONE register means for testing whether said translator unit is presently available for translation;

branching, in response to an output determined by the step of decoding, a chosen one of said set of real-time translation functions;

confirming that a host CPU command has been received, and if affirmative, reading task registers associated with said host CPU;

wherein if the step of decoding determines that a multiplication function is required, branching to provide a said multiplication function;

wherein if the step of decoding determines that a division function is required, branching to provide a said division function;

wherein if the step of decoding determines that a block address is to be converted to a cylinder-head-sector address, branching to provide a block to address conversion;

wherein if the decoding step determines that a cylinder-head-sector address is to be converted to a block address, confirming receipt of said host CPU command, reading said task registers associated with said host CPU, and branching to provide a block address conversion; and

setting said DONE register upon translation completion.

13. The method of claim 12, wherein a said address conversion is carried out using an equation given by:

space="preserve" listing-type="equation">X/Y=t0+r0

space="preserve" listing-type="equation">t0/Z=t1+r1

space="preserve" listing-type="equation">t1+W=r2

where X is said block address, Y is a sector and track number, t0 is an integer quotient resulting from dividing X/Y, t0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a zone.

14. The method of claim 12, wherein a said block address conversion is carried out using an equation given by;

space="preserve" listing-type="equation">block address=((((C*Nh)+H)*Ns)+S-1)

where C is a head number, Nh is a head and drive number, H is a head number, Ns is a sector and track number, and S is a sector number.