Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic

• US 5,715,476 A
• Filed: 12/29/1995
• Issued: 02/03/1998
• Est. Priority Date: 12/29/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kundu, Aniruddha, Khandekar, Narendra
• Primary Examiner(s): Meky, Moustafa M.
• Application Number:
  US08/580,748
• Time in Patent Office: 767 Days
• Field of Search: 395/821, 395/825, 395/834, 395/405, 395/427, 395/454, 395/855, 395/309, 395/401, 395/800, 365/189.01, 365/189.04, 365/230.03, 365/230.04, 365/230.09, 365/233, 365/238.5, 365/239
• US Class Current: 710/35
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Memory access control logic for controlling sequential and toggle mode burst accesses to a memory in a computer system using toggle mode automatic increment logic. The memory access control logic of the invention controls the sequence in which locations of a memory are accessed during a memory burst access operation wherein the burst access sequence is determined by an order in which a burst access starting address is incremented. Toggle increment logic for incrementing a starting address in a toggle sequence is included in the computer system in which the memory access control logic of the invention is used. An input bus receives a burst access request and a burst access starting address indicating a first memory location to be accessed in response to the burst access request from a device in the computer system. Additional logic determines whether the device requires a linear increment sequence or a toggle increment sequence for the burst access. Control logic controls the toggle increment logic to increment the starting address in a linear sequence in response to determining that the first device requires a linear increment sequence.

Claims

1. An apparatus for controlling the order in which locations of a memory in a computer system are accessed during a burst access operation, the order being determined by a sequence in which a burst access starting address is incremented, the computer system including toggle increment logic to increment an address in a toggle sequence, the apparatus comprising:

an input bus to receive burst access requests and corresponding starting addresses from a plurality of devices in the computer system, each starting address indicating a first memory location to be accessed in response to the corresponding burst access request, each of the plurality of devices requiring either a linear or a toggle address increment sequence; and

sequence control logic coupled to the input bus and to be coupled to the toggle increment logic to control the toggle increment logic to increment the starting address in a linear sequence in response to a burst access request from a device requiring a linear address increment sequence, the sequence control logic ignoring accesses to memory locations having addresses indicated by the toggle increment logic which are not included in the linear sequence.

2. The apparatus as set forth in claim 1 wherein the memory is a synchronous dynamic random access memory (SDRAM).

3. The apparatus as set forth in claim 2 wherein the toggle increment logic is configured on the SDRAM.

4. The apparatus as set forth in claim 3 wherein the SDRAM includes a mode register having a burst length field to store a burst length indicating a number of memory locations to be accessed during a burst access operation.

5. The apparatus as set forth in claim 4 wherein the toggle increment logic increments an address in one of a plurality of toggle address increment sequences, the particular toggle address increment sequence being selected by the burst length indicated in the mode register and a value of a predetermined number of least significant bits of the address to be incremented.

6. The apparatus as set forth in claim 5 wherein the required linear address increment sequence for a device requiring a linear address increment sequence during a burst access is determined by the burst length indicated in the mode register and a value of the predetermined number of least significant bits of the starting address corresponding to the burst access request from the device requiring a linear address increment sequence.

7. The apparatus as set forth in claim 1 further including logic for combinatorially changing a value of a predetermined number of least significant bits of the starting address to select one or more of a plurality of toggle address increment sequences to combine to to increment the starting address in the linear sequence.

8. The apparatus as set forth in claim 1 wherein the computer system includes a processor communicating with the memory over a host bus and one or more peripheral devices communicating with the memory on a peripheral component interconnect (PCI) bus, and wherein a linear access order is required for burst access requests from the devices coupled to the PCI bus and a toggle access order is required for burst access requests from the processor coupled to the host bus.

9. The apparatus as set forth in claim 1 wherein the sequence control logic further combines a plurality of toggle increment sequences to produce the linear sequence if the linear and toggle increment sequences corresponding to the starting address are different from each other.

10. A method for controlling the order in which locations of a memory in a computer system are accessed during a burst access operation, the order being either a linear order or a toggle order, the order being determined by a sequence in which a burst access starting address is incremented, the computer system including toggle increment logic for incrementing an address in a toggle sequence, the method comprising the steps of:

receiving a burst access request and a burst access starting address from a first device in the computer system, the starting address indicating a first memory location to be accessed during the burst access operation performed in response to the burst access request;

determining whether the first device requires a linear or a toggle address increment sequence for the burst access operation;

controlling the toggle increment logic by a sequence control logic to increment the starting address in a linear sequence if the first device is determined to require a linear burst access sequence; and

ignoring an access to a particular memory location by the sequence control logic if the toggle increment logic increments the starting address to access the location and the location is not required to be accessed during the burst access operation.

11. The method as set forth in claim 10 wherein the memory is an SDRAM.

12. The method as set forth in claim 11 wherein the toggle increment logic is configured on the SDRAM.

13. The method as set forth in claim 12 wherein the SDRAM includes a mode register to store a burst length indicating a number of memory locations to be accessed during a burst access operation.

14. The method as set forth in claim 13 wherein the toggle increment logic increments an address in one of a plurality of toggle address increment sequences depending on the burst length indicated in the mode register and a value of a predetermined number of least significant bits of the address to be incremented.

15. The method as set forth in claim 14 wherein if the first device is determined to require a linear address increment sequence, the required linear address increment sequence is determined by the burst length and a value of the predetermined number of least significant bits of the starting address.

16. The method as set forth in claim 15 further including a step of combinatorially changing the value of the predetermined number of least significant bits of the starting address to select one or more of the plurality of toggle address increment sequences in order to duplicate the required linear address increment sequence.

17. The method as set forth in claim 15 wherein the burst length is four data words and the predetermined number of least significant bits determining the value is two.

18. The method as set forth in claim 10 wherein the computer system includes a processor communicating with the memory over a host bus and at least one peripheral device communicating with the memory on a PCI bus, and wherein the step of determining is responsive to a source of the burst access request to determine that the device requires a linear access order if the burst access request is received from the PCI bus and a toggle access order if the burst access request is received from the host bus.

19. The method as set forth in claim 10 wherein the step of controlling includes a step of combining a plurality of toggle increment sequences to produce the linear sequence if the linear and toggle increment sequences corresponding to the starting address are different from each other.

20. A computer system comprising:

a processor;

a host bus coupled to the processor for communicating information;

a memory coupled to the host bus;

a peripheral bus coupled to the memory;

toggle increment logic coupled to the memory, the host bus and the peripheral bus to increment an address in a toggle increment sequence; and

smart increment logic coupled to the memory to control the sequence of a burst access to the memory in response to a burst access request and a burst access starting address received from the host bus or the peripheral bus, the smart increment logic controlling the toggle increment logic to increment the burst access starting address in a linear increment sequence if the burst access request is received from the peripheral bus, the smart increment logic ignoring accesses indicated by addresses from the toggle increment logic which are not included in the linear sequence.

21. The computer system as set forth in claim 20 wherein the peripheral bus is a peripheral component enterconnect (PCI) bus.

22. The computer system as set forth in claim 20 wherein a particular toggle address increment sequence selected by the toggle increment logic is determined by a burst length set in a burst length register coupled to the memory and a value of a predetermined number of least significant bits of the burst access starting address.

23. The computer system as set forth in claim 22 further including combinatorial logic coupled to the toggle increment logic to combinatorially change the burst access starting address to select one or more toggle address increment sequences in order to produce the linear address increment sequence.

24. The computer system as set forth in claim 20 wherein the smart increment logic further combines a plurality of toggle increment sequences to produce the linear sequence if the linear and toggle increment sequences corresponding to the starting address are different from each other.

25. An apparatus for determining the addresses of memory locations to be accessed in response to linear and toggle memory burst access requests specifying a starting address while in a toggle increment mode, the apparatus comprising:

toggle increment control logic to increment the starting address in one of a plurality of toggle sequences, the particular toggle sequence depending on the starting address, the toggle increment control logic operative in the toggle increment mode; and

smart increment control logic coupled to control the toggle increment control logic to increment the starting address in a linear sequence while in the toggle increment mode in response to a linear burst access request, the smart increment control logic using a plurality of toggle increment sequences to produce a linear sequence if the linear and toggle increment sequences corresponding to the starting address are different, the smart increment control logic ignoring addresses indicated by a toggle sequence provided by the toggle increment control logic which are not included in the linear sequence.