Method for making a ferroelectric device

• US 5,716,875 A
• Filed: 03/01/1996
• Issued: 02/10/1998
• Est. Priority Date: 03/01/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Zurcher, Peter, Jain, Ajay, Jones, Robert E. Jr., Chu, Peir-Yung
• Primary Examiner(s): Niebling, Jon
• Assistant Examiner(s): CHANG, JONI YUK YING
• Application Number:
  US08/609,697
• Time in Patent Office: 711 Days
• Field of Search: 438/3, 438/210, 438/240, 438/296
• US Class Current: 438/3
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A method for forming CMOS transistors and ferroelectric capacitors on a single substrate (10) with improved yield begins by forming CMOS transistors (37a, 37b, 40, 42). A hydrogen anneal using 4-5% hydrogen and a remainder nitrogen is performed to reduce dangling atomic bonds at the gate dielectric/substrate interface of the transistors (37a, 37b, 40, 42). A silicon nitride layer (48) is then deposited over the transistors and on the backside of the wafer substrate (10) in order to substantially encapsulate the effects of the hydrogen anneal to the CMOS transistors (37a, 37b, 40, 42). Ferroelectric capacitor layers (54, 58, 60, 62, 64) are formed overlying the nitride layer (48) where the ferroelectric capacitor layers (54, 58, 60, 62, 64) are oxygen annealed in pure O₂. The nitride layer (48) prevents the transistor hydrogen anneal from damaging the ferroelectric material by containing the hydrogen.

Claims

1. A method for forming a semiconductor device, the method comprising the steps of:

providing a substrate;

forming a plurality of transistors overlying the substrate;

exposing the plurality of transistors to a hydrogen anneal;

forming a barrier layer overlying the plurality of transistors;

forming ferroelectric devices overlying the barrier layer;

exposing the ferroelectric devices to an oxygen anneal; and

wherein the barrier layer prevents the hydrogen anneal from significantly adversely affecting the ferroelectric devices.

2. The method of claim 1 wherein the step of forming ferroelectric devices overlying the barrier layer comprises:

forming the ferroelectric devices as ferroelectric capacitors which are selectively coupled to selected transistors within the plurality of transistors to form nonvolatile memory cells.

3. The method of claim 2 wherein the step of forming the ferroelectric devices as ferroelectric capacitors comprises:

forming contact openings through the barrier layer between the ferroelectric capacitors and the selected transistors; and

forming an electrical contact between the ferroelectric capacitors and the selected transistors, the electrical contact comprising a tantalum nitride portion.

4. The method of claim 1 wherein the step of forming a barrier layer comprises:

forming the barrier layer as a silicon nitride layer.

5. The method of claim 1 wherein the semiconductor device is formed on a semiconductor wafer and the step of forming a barrier layer comprises:

depositing the barrier layer both overlying the plurality of transistors and adjacent a sidewall of the semiconductor wafer.

6. The method of claim 1 wherein the semiconductor device is formed on a semiconductor wafer and the step of forming a barrier layer comprises:

depositing the barrier layer both overlying the plurality of transistors on a top surface of the semiconductor wafer and adjacent a back surface of the semiconductor wafer.

7. The method of claim 1 wherein the step of forming ferroelectric devices comprises:

forming the ferroelectric devices wherein the ferroelectric devices comprise a material selected from a group consisting of;

lead zirconate titanate (PZT), barium titanate, calcium titanate, bismuth titanate, strontium titanate, lead zirconate, lead lanthanum zirconate titanate, lead niobium zirconate titanate, lead lanthanum niobium zirconate titanate, strontium bismuth tantalum oxide (Y1), strontium bismuth niobate, strontium bismuth niobate tantalate, barium strontium titanate, and lead titanate.

8. The method of claim 1 wherein the step of forming ferroelectric devices comprises:

forming the ferroelectric devices wherein the ferroelectric devices comprise a region of ferroelectric strontium bismuth tantalum oxide.

9. The method of claim 1 wherein the step of forming ferroelectric devices comprises:

forming the ferroelectric devices as capacitors having two capacitor electrodes wherein one of the two capacitor electrodes comprises a titanium oxide region and a platinum region.

10. The method of claim 1 wherein the step of exposing the plurality of transistors to a hydrogen anneal comprises:

exposing the plurality of transistors to an ambient environment which comprises hydrogen and nitrogen.

11. The method of claim 10 wherein the step of exposing the plurality of transistors to a hydrogen anneal comprises:

heating the ambient environment to a temperature between 300°

C. and 450°

C.

12. The method of claim 1 wherein the step of exposing the plurality of transistors to a hydrogen anneal comprises:

exposing the plurality of transistors to an ambient environment which contains 4-5% hydrogen and a remainder of nitrogen.

13. The method of claim 12 wherein the step of exposing the plurality of transistors to a hydrogen anneal comprises:

using hydrogen in the ambient environment to bind dangling Si bonds at a gate-oxide-to-substrate interface of the plurality of transistors.

14. The method of claim 1 wherein a first subset of the plurality of transistors are used to form a microcontroller central processing unit (CPU) and a second subset of the plurality of transistors are coupled to the ferroelectric devices to form a ferroelectric memory array for the microcontroller central processing unit (CPU).

15. The method of claim 1 wherein the plurality of transistors contain both NMOS transistors and PMOS transistors in order to form CMOS circuitry.

16. The method of claim 1 wherein the step of providing a substrate comprises:

providing a silicon on insulator (SOI) substrate.

17. A method for forming a semiconductor device, the method comprising the steps of:

providing a substrate;

forming a plurality of CMOS transistors overlying the substrate wherein the plurality of CMOS transistors have a gate-oxide-to-substrate interface;

annealing the plurality of CMOS transistors using a hydrogen anneal comprising 3-7% hydrogen and a remainder nitrogen to bind atomic dangling Si bonds at the gate-oxide-to-substrate interface;

encapsulating the plurality of CMOS transistors via a silicon nitride barrier layer; and

forming ferroelectric capacitors overlying the silicon nitride barrier layer wherein the silicon nitride barrier layer protects the ferroelectric capacitors from adverse affects of the hydrogen anneal.

18. The method of claim 17 wherein the semiconductor device is formed on a top surface of a semiconductor wafer and the step of encapsulating comprises:

forming the silicon nitride barrier layer on both the top surface of the semiconductor wafer and a back surface of the semiconductor wafer.

19. The method of claim 17 further comprising:

annealing the ferroelectric capacitors in an oxygen ambient within a temperature range of 300°

C. to 500°

C. to improve yield of the ferroelectric capacitors, the silicon nitride barrier layer protecting the plurality of CMOS transistors from the oxygen ambient.

20. The method of claim 17 further comprising:

forming contact openings between selected CMOS transistors among the plurality of CMOS transistors and the ferroelectric capacitors; and

electrically coupling the selected CMOS transistors to the ferroelectric capacitors via a conductive material which comprises tantalum nitride.

21. The method of claim 17 wherein the step of providing a substrate comprises:

providing a substrate that is a silicon on insulator substrate (SOI).

22. A method for forming a semiconductor device, the method comprising the steps of:

providing a substrate;

forming a plurality of CMOS transistors overlying the substrate wherein the plurality of CMOS transistors have a gate-oxide-to-substrate interface;

annealing the plurality of CMOS transistors via a hydrogen anneal;

encapsulating the plurality of CMOS transistors via a silicon nitride barrier layer;

forming ferroelectric capacitors overlying the silicon nitride barrier layer wherein the silicon nitride barrier layer protects the ferroelectric capacitors from adverse affects of the hydrogen anneal and;

annealing the ferroelectric capacitors in an oxygen ambient within a temperature range of 300°

C. to 500°

C. to improve yield of the ferroelectric capacitors, the silicon nitride barrier layer protecting the plurality of CMOS transistors from adverse affects of the oxygen ambient.

23. The method of claim 22 wherein the semiconductor device is formed on a top surface of a semiconductor wafer and the step of encapsulating comprises:

forming the silicon nitride barrier layer on both the top surface of the semiconductor wafer and a back surface of the semiconductor wafer.

24. The method of claim 22 further comprising:

forming contact openings between selected CMOS transistors among the plurality of CMOS transistors and the ferroelectric capacitors; and

electrically coupling the selected CMOS transistors to the ferroelectric capacitors via a conductive material which comprises tantalum nitride.

25. The method of claim 22 wherein the step of providing a substrate comprises:

providing a substrate that is a silicon on insulator substrate (SOI).

26. A method for forming a ferroelectric device, the method comprising the steps of:

forming a ferroelectric capacitor having a first electrode, a second electrode, and a ferroelectric material separating the first electrode and the second electrode;

forming a dielectric layer over the ferroelectric capacitor;

forming at least one metal contact to one of either the first electrode or the second electrode of the ferroelectric capacitor; and

exposing the ferroelectric material to an oxygen anneal to repair the ferroelectric material after the at least one metal contact is formed.

27. The method of claim 26 wherein the step of forming at least one metal contact comprises:

forming the at least one metal contact from a metal material which comprises aluminum.

28. The method of claim 26 further comprising:

forming at least one transistor before forming the ferroelectric capacitor;

annealing the at least one transistor in an environment which contains hydrogen; and

depositing a nitride layer to contain the hydrogen from substantial access to the ferroelectric material.