Low insertion loss switch
First Claim
1. A switching circuit comprising:
- a field effect transistor having a drain and a source, a path between said drain and said source serving as a signal path;
a high-impedance element having a first terminal connected to a gate terminal of said field effect transistor and second terminal connected to a bias control circuit,said bias control circuit comprised of first and second diodes disposed in a forward direction from corresponding first and second control terminals; and
a matching circuit comprising a first capacitor connected between said drain terminal of said field effect transistor and a ground.
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Accused Products
Abstract
A switching circuit further decreasing the insertion loss. The first capacitor is connected between the drain terminal of the field effect transistor and the ground and/or the second capacitor is connected between the source terminal of the field effect transistor and the ground, and the capacitances of the first and/or second capacitors are set to optimum values. Accordingly, the switching circuit can be easily obtained which is low in insertion loss at a desired frequency. Besides, since a bias circuit for generating bias voltage from control voltage which is applied to the two control terminals of a switching circuit using a field effect transistor is provided, a switching circuit which does not need exclusive bias terminals and is superior in isolation property can be realized.
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Citations
12 Claims
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1. A switching circuit comprising:
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a field effect transistor having a drain and a source, a path between said drain and said source serving as a signal path; a high-impedance element having a first terminal connected to a gate terminal of said field effect transistor and second terminal connected to a bias control circuit, said bias control circuit comprised of first and second diodes disposed in a forward direction from corresponding first and second control terminals; and a matching circuit comprising a first capacitor connected between said drain terminal of said field effect transistor and a ground. - View Dependent Claims (2, 3)
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4. A switching circuit comprising:
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a field effect transistor having a drain and a source, a path between said drain and said source serving as a signal path; a bias voltage generating means, having first and second control terminals to which first and second voltages having different values are alternately applied, for generating a bias voltage on the basis of said first and second voltages applied to said first and second control terminals, wherein said bias voltage is applied to said field effect transistor; and a high-impedance element connected between a gate terminal of said field effect transistor and said first control terminal. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11)
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12. A switching circuit comprising:
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a field effect transistor having a drain and a source, a path between said drain and said source serving as a signal path; a high-impedance element having a first terminal connected to a gate terminal of said field effect transistor and second terminal connected to a bias control circuit, said bias control circuit comprised of first and second diodes disposed in a forward direction from corresponding first and second control terminals; and a matching circuit comprising a first capacitor connected between said source terminal of said field effect transistor and a ground.
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Specification