Graphic processing having apparatus for outputting FIFO vacant information

• US 5,717,440 A
• Filed: 12/06/1994
• Issued: 02/10/1998
• Est. Priority Date: 10/06/1986
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi Engineering Co.,Ltd (Hitachi, Ltd.), Hitachi, Ltd.
• Inventors: Sato, Jun, Matsuo, Shigeru, Yokota, Yoshikazu, Sone, Takashi, Kikuchi, Masahiko, Katsura, Koyo
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/355,151
• Time in Patent Office: 1,162 Days
• Field of Search: 395/162-166, 395/513, 395/501, 395/502, 395/507, 395/522, 345/185, 345/196
• US Class Current: 345/558
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 11/203 Drawing of straight lines or curves
• CPC Class Codes: G09G 5/024 using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

A graphic processing system including a main memory for storing a program and information correspond to pixels, a main processor for effecting an execution processing of a program transferred from the main memory or from an external device so as to control the system, display/output devices such as a CRT device and a printer for outputting graphic information attained by controlling pixels arranged in a plurality of dimensions, a frame buffer for storing information corresponding to pixels outputted to the display/output devices, and a graphic processor for receiving a command and parameter information transferred from the main memory and/or the main processor, for generating character and graphic data in accordance with a predetermined processing procedure and for performing a transfer control including an execution of a drawing processing to transfer generated data through first and second address buses and first and second data buses to the main memory and/or the frame buffer, respectively. The system includes a bus connection switch circuit to be controlled by the graphic processor to effect a connection control between the first and second address buses and between the first and second data buses so as to enable execution of a drawing processing in the main memory connected to a bus on the main processor side and a data transfer between the main memory and the frame buffer.

Claims

1. A graphic processing system for controlling a display, comprising:

a central processing unit (CPU) which controls said graphic processing system by outputting commands and parameters for causing a character and graphics to be drawn on said display or an operation to be performed on data to be displayed on said display; and

a processor which receives said commands and parameters and draws a character and graphics on said display or performs an operation on data to be displayed on said display in response to said commands and parameters;

wherein said processor includes a first-in first-out (FIFO) buffer for storing said commands and parameters received from said CPU, said FIFO buffer includes a plurality of storage areas, and

wherein said processor reads out said commands and parameters from said FIFO buffer, draws a character and graphics on said display or performs an operation on data to be displayed on said display in response to said commands and parameters and outputs information to said CPU representing a number of empty storage areas in said FIFO buffer thereby requesting said CPU to output an amount of commands and parameters corresponding to the number of said empty storage areas represented by said information so as to fill all of said empty storage areas in said FIFO buffer.

2. A graphic processing method according to claim 1, wherein said CPU includes a FIFO status register for holding information relating to the number of said empty storage areas in said FIFO buffer from said FIFO buffer, said information being used to control the reading out of the commands and parameters in accordance with the number of said empty storage areas which varies with inputting and outputting of data into or from said FIFO buffer.

3. A graphic processing method according to claim 2, wherein said information relating to the number of said empty storage areas in the FIFO buffer represents a storage capacity of an area in which data are not held in the FIFO buffer.

4. A graphic processing method according to claim 3, wherein said storage capacity is defined by the number of words of data.

5. A graphic processing method of controlling a display in response to commands and parameters output from a central processing unit (CPU), said commands and parameters cause a character and graphics to be drawn on said display or an operation to be performed on data to be displayed on said display, said graphic processing method comprising the steps of:

storing in a first-in first-out (FIFO) buffer said commands and parameters from said CPU, said FIFO buffer includes a plurality of storage areas;

reading out said commands and parameters from said FIFO buffer, drawing a character or graphics on said display or performing an operation on data to be displayed on said display in response to said commands and parameters; and

outputting information to said CPU representing a number of empty storage areas in said FIFO buffer thereby requesting said CPU to output an amount of commands and parameters corresponding to the number of said empty storage areas represented by said information so as to fill all of said empty storage areas in said FIFO buffer.

6. A graphic processing method according to claim 5, wherein said CPU includes a first-in first-out (FIFO) status register for holding information relating to the number of empty storage areas in said FIFO buffer, said information being used to control the reading out of the commands and the parameters in accordance with the number of empty storage areas which varies with inputting and outputting of data into or from said FIFO buffer.

7. A graphic processing method according to claim 6, wherein said information relating to the of empty storage areas in the FIFO represents a storage capacity of area in which data are not held in the FIFO buffer.

8. A graphic processing method according to claim 7, wherein said storage capacity is defined by the number of words of data.

9. A graphic processing method according to claim 5, further comprising the steps of:

providing an indication of the status of the number of empty storage areas in said FIFO buffer wherein the number empty storage areas varies with inputting and outputting of data to or from the FIFO buffer; and

holding in a FIFO status register the indication of status;

wherein said CPU controls the reading out of the commands and parameters based on the information held in said FIFO status register.

10. A graphic processing method according to claim 9, wherein said information relating to the number of empty storage areas in the FIFO represents a storage capacity of an area in which data are not held in the FIFO buffer.

11. A graphic processing method according to claim 10, wherein said storage capacity is defined by the number of words of data.

12. A graphic processor for controlling a display in response to commands and parameters output from a central processing unit (CPU), said commands and parameters cause a character and graphics to be drawn on said display or an operation to be performed on data to be displayed on said display, said graphic processor comprising:

a first-in first-out (FIFO) buffer for storing said commands and parameters from said CPU, said FIFO buffer includes a plurality of storage areas; and

means for reading out said commands and parameters from said FIFO buffer, drawing a character and graphics on said display or performing an operation on data to be displayed on said display in response to said commands and parameters, and outputting information to said CPU representing a number of empty storage areas in said FIFO buffer thereby requesting said CPU to output an amount of commands and parameters corresponding to the number of said empty storage areas represented by said information so as to fill all of said empty storage areas in said FIFO buffer.

13. A graphic processor according to claim 12, wherein said CPU includes a first-in first-out (FIFO) status register for holding information relating to the number of empty storage areas in said FIFO buffer, said information being used to control the reading out of the commands and the parameters in accordance with the number of empty storage areas which varies with inputting and outputting of data into or from said FIFO buffer.

14. A graphic processor according to claim 13, wherein said information relating to the number of empty storage areas in the FIFO buffer represents a storage capacity of an area in which data are not held in the FIFO buffer.

15. A graphic processor according to claim 14, wherein said storage capacity is defined by the number of words of data.

16. A graphic processor according to claim 12, further comprising:

a counter for providing an indication of the status of the number of empty storage areas in said FIFO buffer, wherein the number of empty storage areas varies with inputting and outputting of data to or from the FIFO buffer; and

a FIFO status register for holding the indication of status;

wherein said CPU controls the reading out of the commands and parameters based on the information held in said FIFO status register.

17. A graphic processor according to claim 16, wherein said information relating to the number of empty storage areas in the FIFO buffer includes information indicating a storage capacity representing an area in which data are not held in the FIFO buffer.

18. A graphic processor according to claim 17, wherein said storage capacity is defined by the number of words of data.

19. A graphic processor for responding to commands and parameters output from a central processing unit (CPU), comprising:

an execution unit for drawing a character and graphics or performing an operation in response to said commands and parameters;

a first-in first-out (FIFO) buffer for storing commands and parameters from said CPU, said FIFO buffer includes a plurality of storage areas; and

means for reading out said commands and parameters stored in said FIFO buffer, supplying said read out commands and parameters to said execution unit, and outputting information to said CPU representing a number of empty storage areas in said FIFO buffer thereby requesting said CPU to output an amount of commands and parameters corresponding to the number of said empty storage areas represented by said information so as to fill all of said empty area in said FIFO buffer.

20. A graphic processor according to claim 19, wherein said CPU includes a first-in first-out (FIFO) status register for holding information relating to the number of empty storage areas in said FIFO buffer, said information being used to control the reading out of the commands and the parameters in accordance with the number of empty storage areas which varies with inputting and outputting of data into or from said FIFO buffer.

21. A graphic processor according to claim 20, wherein said information relating to the number of empty storage areas in the FIFO buffer represents a storage capacity of an area in which data are not held in the FIFO buffer.

22. A graphic processor according to claim 21, wherein said storage capacity is defined by the number of words of data.

23. A graphic processor according to claim 19, further comprising:

a counter for providing an indication of the status of the number of empty storage areas in said FIFO buffer wherein the number of empty storage areas varies with inputting and outputting of data to or from the FIFO buffer; and

a FIFO status register for holding the indication of status;

wherein said CPU controls the reading out of the commands and parameters based on the information held in said FIFO status register.

24. A graphic processor according to claim 23, wherein said information relating to the number of empty storage areas in the FIFO buffer represents a storage capacity representing an area in which data are not held in the FIFO buffer.

25. A graphic processor according to claim 24, wherein said storage capacity is defined by the number of words of data.

26. A graphic processing system comprising:

a central processing unit (CPU); and

a processor for receiving commands and parameters supplied from said CPU for drawing a character and graphics and performing an operation;

wherein said processor includes a first-in first-out (FIFO) buffer for storing said commands and parameters therein, said FIFO buffer includes a plurality of storage areas, and said CPU reads out information from said FIFO buffer representing a number of empty storage areas, in said FIFO buffer and outputs an amount of commands and parameters corresponding to the number of empty storage areas in said FIFO buffer represented by said information so as to fill all of said empty storage areas in said FIFO buffer.

27. A graphic processor according to claim 26, wherein said CPU includes a FIFO status register for holding information relating to the number of said empty storage areas in said FIFO buffer from said FIFO buffer, said information being used to control the reading out of the commands and parameters in accordance with the number of said empty storage areas which varies with inputting and outputting of data into or from said FIFO buffer.

28. A graphic processor according to claim 27, wherein said information relating to the number of said empty storage areas in the FIFO buffer represents a storage capacity of an area in which data are not held in the FIFO buffer.

29. A graphic processor according to claim 28, wherein said storage capacity is defined by the number of words of data.

30. A graphic processor according to claim 26, further comprising:

a counter for providing an indication of the status of the number of empty storage areas in said FIFO buffer wherein the number of empty storage areas varies with inputting and outputting of data to or from the FIFO buffer; and

a FIFO status register for holding the indication of status;

wherein said CPU controls the reading out of the commands and parameters based on the information held in said FIFO status register.

31. A graphic processor according to claim 30, wherein said information relating to the number of empty storage areas in the FIFO buffer includes information indicating a storage capacity representing an area in which data are not held in the FIFO buffer.

32. A graphic processor according to claim 31, wherein said storage capacity is defined by the number of words of data.

33. A graphic processing system comprising:

a central processing unit (CPU); and

a graphic processor for receiving commands and parameters supplied from said CPU for drawing a character and graphics and performing an operation;

wherein said graphic processor, including a first-in first-out (FIFO) buffer for storing said commands and parameters therein, said FIFO buffer includes a plurality of storage areas, determines whether an empty storage area exists in said FIFO buffer and a number of said empty storage areas, and outputs information indicating that an empty area exists in said FIFO buffer and the number of said empty storage areas to said CPU thereby requesting said CPU to output an amount of commands and parameters corresponding to the number of said empty storage areas in said FIFO buffer represented by said information so as to fill all of said empty storage areas in said FIFO buffer.