Burst EDO memory device with maximized write cycle timing

• US 5,717,654 A
• Filed: 02/10/1997
• Issued: 02/10/1998
• Est. Priority Date: 02/10/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): LE, VU ANH
• Application Number:
  US08/797,339
• Time in Patent Office: 365 Days
• Field of Search: 365/233.5, 365/233, 365/189.05, 365/189.01, 365/193, 365/230.01
• US Class Current: 365/233.5
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access, reset the burst length counter and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies.

Claims

1. A memory device having a plurality of memory elements, each of the elements having an associated address, the memory device adapted to switch control of a write operation between a write command and an address latch signal during a write operation, the memory comprising:

addressing circuitry adapted to receive a first address in response to a first transition of the address latch signal, and further adapted to generate a second address in response to a subsequent transition of the address latch signal; and

a write cycle command latch to store a latched write command in response to the first transition of the address latch signal, the address latch signal initiating a memory access cycle.

2. The memory device of claim 1, wherein the write cycle command latch is cleared in response to the first transition of the address latch signal prior to storing the write command.

3. The memory device of claim 1, wherein the write cycle command latch stores the write command until the subsequent transition of the address latch signal.

4. The memory device of claim 1, further comprising:

a switching circuit, responsive to an output of the write cycle command latch and the address latch signal, to a control a data storage operation of the memory device.

5. The memory device of claim 4, wherein the write cycle command latch and the switching circuit are irresponsive to the write command while the write cycle command latch is in a latched state.

6. A memory device having an array of memory elements, adapted to store data in response to a write operation, and an address latch to receive a first address in response to an address latch signal, the memory device comprising:

an address generating circuit responsive to the address latch signal and to the first address to generate a second address, wherein the second address is used to access the array; and

a write control circuit adapted to switch control of the write operation from a write command signal to the address latch signal during a write operation, wherein the write command signal initiates the write operation, and the access cycle signal terminates the write operation.

7. The memory device of claim 6, wherein the write control circuit is further adapted to initiate a subsequent write operation in response to the address latch signal after terminating a first write operation.

8. A memory system comprising:

a microprocessor; and

a memory circuit adapted to store and retrieve data in a burst access in response to a memory address received from the microprocessor and in response to control signals, wherein the memory circuit is adapted to latch the memory address and perform a first memory access in response to a first transition of the address latch signal within the burst access and is further adapted to generate an additional memory address and perform a memory access cycle in response to each of a plurality of additional transitions of the address latch signal within a burst access, the memory circuit further comprises a write operation control circuit adapted to switch control of a write operation between a write command signal and an address latch signal during a write operation, wherein the write command signal initiates the write operation, and the address latch signal terminates the write operation.

9. The apparatus of claim 8, further comprising a memory access control circuit to generate the address latch signal.

10. The apparatus of claim 8, wherein the microprocessor comprises memory control circuitry to generate the address latch signal.

11. The apparatus of claim 8, wherein data read from the memory address of the memory circuit is provided by the memory circuit to the microprocessor after at least two transitions of the address latch signal in the burst access.

12. The apparatus of claim 11, wherein additional data values from a predetermined sequence of addresses of the memory circuit are provided to the microprocessor in response to additional transitions of the address latch signal after the microprocessor receives data from the memory address.

13. The apparatus of claim 8, wherein the memory circuit comprises dynamic random access memory elements.