Apparatus and method for testing interconnections between semiconductor devices

• US 5,717,701 A
• Filed: 08/13/1996
• Issued: 02/10/1998
• Est. Priority Date: 08/13/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Douskey, Steven Michael, Angelotti, Frank William
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/702,414
• Time in Patent Office: 546 Days
• Field of Search: 324/73 R, 324/158 R, 371/22.1, 371/22.3, 371/22.4, 395/183.06
• US Class Current: 714/30
• CPC Class Codes: G01R 31/31855 Interconnection testing, e.g. crosstalk, shortcircuits

Abstract

A boundary scan register allows for simplified testing of interconnections between integrated circuits. The interconnections between integrated circuits are characterized according to net type. Each net type has one or more mask registers that drive control inputs to each boundary scan register that drives a net of that type. One integrated circuit is configured to drive, while the others are configured to receive. The boundary scan registers are initialized to predetermined values, the mask registers are loaded, and clocks are pulsed to perform the needed tests. The results are then scanned out of the boundary scan registers, and a compression circuit compresses the test results data.

Claims

1. An on-chip boundary scan cell for an integrated circuit comprising:

a data latch that is preloadable with a predetermined value, the data latch having a data input coupled to at least one of a plurality of input/output (I/O) pins on the integrated circuit;

an enable latch that is preloadable with a predetermined value;

a clock gating circuit coupled to at least one mask register for storing data on the data input when indicated by the information in the mask register;

an enable gating circuit coupled to the at least one mask register for driving the output of the data latch onto at least one of the plurality of I/O pins when indicated by the information in the at least one mask register.

2. The boundary scan cell of claim 1 wherein the data latch further comprises a serial clock input, a serial data input, a serial data output, and a data clock input, the data latch storing the state of the serial data input when the serial clock is applied, the data latch outputting its current state on the serial data output when the serial clock is applied, the data latch storing the state of the data input when the data clock input is applied.

3. The boundary scan cell of claim 1 wherein the enable latch comprises a serial clock input, a serial data input, a serial data output, and a parallel data output, the parallel data output controlling a driver coupled to at least one of the plurality of I/O pins, the enable latch storing the state of the serial data input when the serial clock is applied, the enable latch outputting its current state on the serial data output and on the parallel data output when the serial clock is applied.

4. The boundary scan cell of claim 1 wherein the at least one mask register includes a plurality of shift register latches (SRLs), the at least one mask register including a different group of SRLs for controlling different types of nets coupled to the I/O pins of the integrated circuit.

5. The boundary scan cell of claim 1 wherein the clock gating circuit includes a compression circuit for compressing the output of the data latch over a plurality of tests.

6. The boundary scan cell of claim 5 wherein the compression circuit implements a logical exclusive OR (XOR) function.

7. An integrated circuit device comprising:

a plurality of input/output (I/O) pins;

a semiconductor device including operational circuitry coupled to at least one of the plurality of I/O pins; and

boundary scan test circuitry including;

at least one mask register for storing information relating to the testing of a particular net type; and

a plurality of boundary scan cells interposed between the operational circuitry and the plurality of I/O pins to allow testing of interconnections between the integrated circuit device and at least one external integrated circuit, at least one of the plurality of boundary scan cells comprising;

a data latch that is preloadable with a predetermined value, the data latch having a data input coupled to at least one of the plurality of I/O pins;

an enable latch that is preloadable with a predetermined value;

a clock gating circuit coupled to the at least one mask register for storing data on the data input when indicated by the information in the mask register;

an enable gating circuit coupled to the at least one mask register for driving the output of the data latch onto at least one of the plurality of I/O pins when indicated by the information in the at least one mask register.

8. The integrated circuit device of claim 7 wherein the at least one mask register includes a plurality of shift register latches (SRLs), the at least one mask register including a different group of SRLs for controlling different types of nets coupled to the I/O pins of the integrated circuit device.

9. The integrated circuit device of claim 7 wherein the plurality of boundary scan cells form a scan chain, the integrated circuit device further comprising a compression circuit for compressing the test results stored in the scan chain.

10. The integrated circuit device of claim 9 wherein the compression circuit comprises a ones counter.

11. An electronic assembly comprising;

(A) a plurality of integrated circuit devices, each of the plurality of integrated circuit devices comprising;

a plurality of input/output (I/O) pins;

a semiconductor device including operational circuitry coupled to at least one of the plurality of I/O pins; and

boundary scan test circuitry including;

at least one mask register for storing information relating to the testing of a particular net type; and

a plurality of boundary scan cells interposed between the operational circuitry and the plurality of I/O pins in a scan chain to allow testing of interconnections between the integrated circuit device and at least one external integrated circuit, at least one of the plurality of boundary scan cells comprising;

a data latch that is preloadable with a predetermined value, the data latch having a data input coupled to at least one of the plurality of I/O pins;

an enable latch that is preloadable with a predetermined value;

a clock gating circuit coupled to the at least one mask register for storing data on the data input when indicated by the information in the at least one mask register;

an enable gating circuit coupled to the at least one mask register for driving the output of the data latch onto at least one of the plurality of I/O pins when indicated by the information in the at least one mask register;

(B) a plurality of interconnections between the I/O pins of the plurality of integrated circuit devices;

(C) a controller for initializing at least one of the scan chains to ones, for initializing at least one of the scan chains to zeroes, for walking a one through at least one of the scan chains that was initialized to zero, and for walking a zero through at least one of the scan chains that was initialized to one.

12. The electronic assembly of claim 11 further comprising a memory device for storing values for the at least one mask register and for storing expected test results.

13. The electronic assembly of claim 11 wherein the boundary scan test circuitry further comprises a compression circuit for compressing the test results stored in the scan chain.

14. A method for testing the interconnections between a plurality of integrated circuit devices on an electronic assembly, the method including the steps of:

(A) providing the electronic assembly with the plurality of integrated circuit devices thereon, each integrated circuit device including a plurality of boundary scan cells arranged in a scan chain to allow testing of interconnections between the plurality of integrated circuit devices;

(B) providing the interconnections between the plurality of integrated circuit devices, each interconnection comprising a net;

(C) characterizing each net on the circuit board as of a particular net type;

(D) providing at least one mask register for storing information relating to the testing of a particular net type;

(E) designating one of the plurality of integrated circuit devices as the driving device;

(F) designating each of the integrated circuit devices not designated as the driving device as a receiving device;

(G) initializing the scan chain of the driving device to a predetermined logical state;

(H) initializing the scan chain of each receiving device to a predetermined logical state;

(I) loading the at least one mask register with a mask suitable for a particular test; and

(J) applying at least one clock signal to the boundary scan cells to perform the particular test.

15. The method of claim 14 further including the step of:

repeating steps (E) through (J) until each of the integrated circuit devices has been selected as the driving device.

16. The method of claim 14 wherein step (G) initializes the scan chain of the driving device to zero, and wherein the method further comprises the step of:

walking a one through the scan chain of the driving device to detect whether any of the nets are shorted to any other net.

17. The method of claim 14 wherein step (G) initializes the scan chain of the driving device to one, and wherein the method further comprises the step of:

walking a zero through the scan chain of the driving device to detect whether any of the nets are shorted to any other net.

18. The method of claim 14 wherein step (G) initializes the scan chain of the driving device to zero and wherein step (H) initializes the scan chain of each receiving device to one in order to perform a test to determine whether any of the nets are stuck high.

19. The method of claim 14 wherein step (G) initializes the scan chain of the driving device to one and wherein step (H) initializes the scan chain of each receiving device to zero in order to perform a test to determine whether any of the nets are stuck low.

20. A method for testing the interconnections between a plurality of integrated circuit devices on a circuit board, the method including the steps of:

(A) providing the circuit board with the plurality of integrated circuit devices thereon, each integrated circuit device including;

(i) a plurality of input/output (I/O) pins;

(ii) a semiconductor device including operational circuitry coupled to at least one of the plurality of I/O pins;

(iii) at least one mask register for storing information relating to the testing of a particular net type;

(iv) a plurality of boundary scan cells interposed between the operational circuitry and the plurality of I/O pins in a scan chain to allow testing of interconnections between the plurality of integrated circuit devices, the boundary scan cell comprising;

(a) a data latch that is preloadable with a predetermined value, the data latch having a data input coupled to at least one of the plurality of I/O pins;

(b) an enable latch that is preloadable with a predetermined value;

(c) a clock gating circuit coupled to the at least one mask register for storing data on the data input when indicated by the information in the at least one mask register;

(d) an enable gating circuit coupled to the at least one mask register for driving the output of the data latch onto at least one of the plurality of I/O pins on the integrated circuit when indicated by the information in the at least one mask register; and

(e) a compression circuit for compressing the data input over a plurality of tests;

(v) a compression circuit for compressing test results stored in the scan chain;

(B) providing the interconnections between the plurality of integrated circuit devices, each interconnection comprising a net;

(C) characterizing each net on the circuit board as of a particular net type;

(D) providing at least one mask register for storing information relating to the testing of a particular net type;

(E) designating one of the plurality of integrated circuit devices as the driving device;

(F) designating each of the integrated circuit devices not designated as the driving device as a receiving device;

(G) initializing the scan chain of the driving device to a predetermined logical state;

(H) initializing the scan chain of each receiving device to a predetermined logical state;

(I) loading the at least one mask register with a mask suitable for a particular test; and

(J) applying at least one clock signal to the boundary scan cells to perform the particular test.

21. The method of claim 20 further including the step of:

repeating steps (E) through (J) until each of the integrated circuit devices has been selected as the driving device.

22. The method of claim 20 further including the steps of:

scanning out test results data from the scan chains of the integrated circuit devices; and

comparing the test results data to expected test results.