System for wireless transmission and receiving of information through a computer bus interface and method of operation

• US 5,717,725 A
• Filed: 02/21/1995
• Issued: 02/10/1998
• Est. Priority Date: 03/12/1992
• Status: Expired due to Term

• Current Assignee: NTP Incorporated
• Original Assignee: NTP Incorporated
• Inventors: Campana, Thomas J. Jr.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): GHAYOUR, MOHAMMAD H
• Application Number:
  US08/391,555
• Time in Patent Office: 1,085 Days
• Field of Search: 375/347, 370/100.1, 370/105.1, 455/52.1, 455/52.2, 455/52.3, 455/278.1, 455/296, 455/132, 455/65, 455/101, 455/272, 455/273
• US Class Current: 375/347
• CPC Class Codes: H04B 7/10 Polarisation diversity; Directional diversity
• CPC Class Codes: H04H 20/67 Common-wave systems, i.e. using separate transmitters operating on substantially the same frequency
• CPC Class Codes: H04L 1/004 by using forward error control H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00
• CPC Class Codes: H04L 1/02 by diversity reception
• CPC Class Codes: H04L 27/22 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15
• CPC Class Codes: H04W 28/06 Optimizing the usage of the radio link, e.g. header compression, information sizing , discarding information system modifying transmission characteristic according to link quality by modifying frame length H04L1/0007; dynamic adaptation of the packet size for flow control or congestion control H04L47/365
• CPC Class Codes: H04W 68/00 User notification, e.g. alerting and paging, for incoming communication, change of service or the like

Abstract

A system and method is disclosed for transmission of information which is subject to fading by using a RF carrier modulated with a subcarrier modulated with the information. The system has a bus interface which communicates with a digital signal processor which controls the transmitting and receiving circuitry functions. The bus interface is for connection to a computer bus which is connected to a computer which originates information to be transmitted by transmitting circuitry and which receives information from receiving circuitry. The digital signal processor provides first and second encoded information streams each comprising the information to be transmitted with the second stream being delayed by a time delay interval with respect to the first stream which is equal to or greater than the fading interval. The first and second encoded information streams modulate cycles of the subcarrier to produce first and second parallel information streams which are time offset by the time delay interval. The receiving circuitry has a detector for detecting transmitted first and second parallel information streams with the second parallel information stream being delayed from the first parallel information stream by the time delay interval. The digital signal processor determines if faded information is present in the frames of the detected first and second parallel information streams by processing the error correction code therein to determine if a number of bit errors are present which exceed the bit error correction capacity of the error correction code. The digital signal processor places an error marker within the detected first and second parallel information streams to mark each faded information unit and controls replacement of each error marker within at least one of the first and second parallel information streams with replacement data bits within a frame in one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce error free wirelessly transmitted information.

Claims

1. Transmitting circuitry for wireless transmission of information subject to fading for a time interval by modulating a radio frequency carrier with a subcarrier with the information originating from a computer and being transmitted to the transmitter circuitry by an information transmission medium comprising:

an interface for connection to the information transmission medium for receiving the information from the information transmission medium;

a processor, coupled to the information transmission medium, for processing the information received from the interface and in response to the information received from the interface, providing a first encoded information stream which comprises the information to be transmitted and a second encoded information stream which also comprises the information to be wirelessly transmitted with the second encoded information stream being delayed by a time delay interval with respect to the first information stream which is equal to or greater than the time interval of a fade;

an encoder, coupled to the processor and responsive to the first and second encoded information streams, for modulating the subcarrier with the first and second encoded information streams to produce first and second parallel information streams modulating cycles of the subcarrier with the first parallel stream containing the first encoded information stream, with the second parallel stream containing the second encoded information stream and with the first parallel information stream modulating the subcarrier being time displaced from the second parallel information stream modulating the subcarrier by the time delay interval; and

a modulator, coupled to the encoder, for modulating the radio frequency carrier with the modulated subcarrier.

2. Transmitting circuitry in accordance with claim 1 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated by bits at a plurality of separated angular positions.

3. Transmitting circuitry in accordance with claim 1 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the cycles of the subcarrier with pulse width modulation.

4. Transmitting circuitry in accordance with claim 1 wherein:

the first and second encoded information streams each comprise frames of information with each frame having a plurality of bits encoding error correction code and a plurality of bits encoding the information originating from the computer with the error correction code of the first encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the first parallel information stream and the error correction information of the second encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the second parallel information stream.

5. Transmitting circuitry in accordance with claim 4 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated by bits at a plurality of separated angular positions.

6. Transmitting circuitry in accordance with claim 4 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the cycles of the subcarrier with pulse width modulation.

7. Transmitting circuitry in accordance with claim 1 wherein:

the time interval is of a length which would cause receiving circuitry receiving the wireless transmission of information to lose synchronism with transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

8. Transmitting circuitry in accordance with claim 2 wherein:

the time interval is of a length which would cause receiving circuitry receiving the wireless transmission of information to lose synchronism with transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

9. Transmitting circuitry in accordance with claim 3 wherein:

the time interval is of a length which would cause receiving circuitry receiving the wireless transmission of information to lose synchronism with transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

10. Transmitting circuitry in accordance with claim 4 wherein:

the time interval is of a length which would cause receiving circuitry receiving the wireless transmission of information to lose synchronism with transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

11. Transmitting circuitry in accordance with claim 5 wherein:

the time interval is of a length which would cause receiving circuitry receiving the wireless transmission of information to lose synchronism with transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

12. Transmitting circuitry in accordance with claim 6 wherein:

the time interval is of a length which would cause receiving circuitry receiving the wireless transmission of information to lose synchronism with transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

13. A method for wireless transmission of information subject to fading for a time interval with transmitting circuitry by modulating a radio frequency carrier with a subcarrier with the information originating from a computer and being transmitted to the transmitting circuitry by an information transmission medium comprising:

receiving the information from the information transmission medium with an interface;

in response to receiving the information from the interface providing a first encoded information stream which comprises the information to be wirelessly transmitted and a second encoded information stream which also comprises the information to be wirelessly transmitted with the second information stream being delayed by a time delay interval with respect to the first information stream which is equal to or greater than the time interval of a fade;

modulating the subcarrier with the first and second encoded information streams to produce first and second parallel information streams modulated on cycles of the subcarrier with the first parallel information stream containing the first encoded information stream and with the second parallel information stream containing the second encoded information stream and with the first parallel information stream modulating the subcarrier being time displaced from the second parallel stream modulating the subcarrier by the time delay interval; and

modulating the radio frequency carrier with the modulated subcarrier.

14. A method in accordance with claim 13 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated by bits at a plurality of separated angular positions.

15. A method in accordance with claim 13 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the cycles of the subcarrier with pulse width modulation.

16. A method in accordance with claim 13 wherein:

the first and second encoded information streams each comprise frames of information with each frame having a plurality of bits encoding error correction code and a plurality of bits encoding information originating from the computer with the error correction code of the first encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the first parallel information stream and the error correction information of the second encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the second parallel information stream.

17. A method in accordance with claim 14 wherein:

the first and second encoded information streams each comprise frames of information with each frame having a plurality of bits encoding error correction code and a plurality of bits encoding information originating from the computer with the error correction code of the first encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the first parallel information stream and the error correction information of the second encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the second parallel information stream.

18. A method in accordance with claim 15 wherein:

the first and second encoded information streams each comprise frames of information with each frame having a plurality of bits encoding error correction code and a plurality of bits encoding information originating from the computer with the error correction code of the first encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the first parallel information stream and the error correction information of the second encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the second parallel information stream.

19. A method in accordance with claim 13 wherein:

the time interval is of a length which would cause receiving circuitry receiving the wireless transmission of information to lose synchronism with transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

20. A method in accordance with claim 14 wherein:

the time interval is of a length which would cause receiving circuitry receiving the wireless transmission of information to lose synchronism with transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

21. A method in accordance with claim 15 wherein:

the time interval is of a length which would cause receiving circuitry receiving the wireless transmission information to lose synchronism with transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

22. A method in accordance with claim 16 wherein:

the time interval is of a length which would cause receiving circuitry receiving the wireless transmission of information to lose synchronism with transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

23. A method in accordance with claim 17 wherein:

the time interval is of a length which would cause receiving circuitry receiving the wireless transmission of information to lose synchronism with transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

24. A method in accordance with claim 18 wherein:

the time interval is of a length which would cause receiving circuitry receiving the wireless transmission of information to lose synchronism with transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

25. Receiving circuitry for receiving a wireless transmission of information which is subject to fading for a time interval with a radio frequency carrier being modulated with a subcarrier with the subcarrier being modulated with identical first and second encoded information streams each containing the information to produce first and second parallel information streams modulating cycles of the subcarrier with the first parallel information stream containing the first encoded information stream and with the second parallel information stream containing the second encoded information stream with the first and second parallel information streams being wirelessly transmitted with a time delay interval between the first and second parallel information streams modulating the subcarrier which is equal to or greater than the time interval for transmission to a computer by an information transmission medium comprising:

a detector for detecting the transmitted first and second parallel information streams;

a processor, coupled to the detector and responsive to the detected parallel information streams, for determining if faded information is present in at least one of the detected first and second parallel information streams and in response to determined faded information replacing the faded information caused by a fade with replacement information from at least one of the first and second parallel information streams which is time offset at transmission from the faded information by the time delay interval and outputting error free transmitted information including the replacement information; and

an interface, for connection to the information transmission medium and coupled to the processor, for receiving the outputted error free wireless transmission of information and in response to connection to the information transmission medium transmitting the outputted error free wireless transmission of information to the information transmission medium for transmission to the computer.

26. Receiving circuitry in accordance with claim 25 wherein:

the first and second encoded information streams each comprises frames of information with each frame having a plurality of bits encoding error correction code and a plurality of bits encoding the information with the error correction code of the first encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the first parallel information stream and the error correction code of the second encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the second parallel information stream; and

the determination of faded information by the processor is performed by determining that the error correction bits cannot correct an error detected by processing the frames of the first and second parallel information streams with the error correction code using the plurality of bits of error correction code.

27. Receiving circuitry in accordance with claim 25 wherein:

the processor comprises a digital signal processor for processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams; and

wherein

the digital signal processor processes the first and second parallel information streams containing the substituted numerical values for determining if the faded information is present.

28. Receiving circuitry in accordance with claim 26 wherein:

the processor comprises a digital signal processor for processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams; and

wherein

the digital signal processor processes the first and second parallel information streams containing the substituted numerical values for determining if the faded information is present.

29. Receiving circuitry in accordance with claim 25 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated by bits at a plurality of separated angular positions.

30. Receiving circuitry in accordance with claim 25 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the subcarrier with pulse width modulation.

31. Receiving circuitry in accordance with claim 26 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated by bits at a plurality of separated angular positions.

32. Receiving circuitry in accordance with claim 26 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the subcarrier with pulse width modulation.

33. Receiving circuitry in accordance with claim 27 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated by bits at a plurality of separated angular positions.

34. Receiving circuitry in accordance with claim 27 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the subcarrier with pulse width modulation.

35. Receiving circuitry in accordance with claim 28 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated by bits at a plurality of separated angular positions.

36. Receiving circuitry in accordance with claim 28 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the subcarrier with pulse width modulation.

37. Receiving circuitry in accordance with claim 27 wherein:

the digital signal processor calculates the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

38. Receiving circuitry in accordance with claim 37 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

39. Receiving circuitry in accordance with claim 28 wherein:

the digital signal processor calculates the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

40. Receiving circuitry in accordance with claim 39 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

41. Receiving circuitry in accordance with claim 33 wherein:

the digital signal processor calculates the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

42. Receiving circuitry in accordance with claim 41 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

43. Receiving circuitry in accordance with claim 34 wherein:

the digital signal processor calculates the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

44. Receiving circuitry in accordance with claim 43 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

45. Receiving circuitry in accordance with claim 35 wherein:

the digital signal processor calculates the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

46. Receiving circuitry in accordance with claim 45 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

47. Receiving circuitry in accordance with claim 36 wherein:

the digital signal processor calculates the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

48. Receiving circuitry in accordance with claim 47 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

49. A method of receiving a wireless transmission of information subject to fading for a time interval with receiving circuitry with a radio frequency carrier modulated with a subcarrier with the subcarrier being modulated with first and second encoded identical information streams to produce first and second parallel information streams modulating cycles of the subcarrier with the first parallel information stream containing the first encoded information stream and with the second parallel information stream containing the second encoded information stream with the parallel information streams being transmitted with a time delay interval between the parallel streams modulating the subcarrier which is equal to or greater than the time interval for transmission to a computer through an information transmission medium comprising the steps:

detecting the first and second parallel information streams which have been transmitted with the radio frequency carrier;

determining if faded information is present in at least one of the detected first and second parallel information streams and in response to determined faded information replacing the faded information caused by a fade with information from one of the first and second parallel information streams which is time offset from the faded information by the time delay interval and outputting error free transmitted information including the replacement information;

receiving the outputted error free information with an interface; and

transmitting the error free transmitted information from the interface to the information transmission medium and processing the error free transmitted information with a computer coupled to the information transmission medium.

50. A method of receiving a wireless transmission in accordance with claim 49 wherein:

the first and second encoded information streams each comprises frames of information with each frame having a plurality of bits encoding error correction code and a plurality of bits encoding the information with the error correction code of the first encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the first parallel information stream and the error correction code of the second encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the second parallel information stream; and

the determination if faded information is performed by determining that the error correction bits cannot correct an error detected by processing frames of the first and second parallel information streams with the error correction code using the plurality of error correction bits.

51. A method of receiving a wireless transmission in accordance with claim 49 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams; and

wherein

the first and second parallel information streams containing the substituted numerical values are processed for determining if the faded information is present.

52. A method of receiving a wireless transmission in accordance with claim 50 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams; and

wherein

the first and second parallel information streams containing the substituted numerical values are processed for determining if the faded information is present.

53. A method of receiving a wireless transmission in accordance with claim 49 wherein:

bits of each of the first and second parallel information streams are modulated on cycles of the subcarrier with each cycle of the subcarrier being modulated with bits at a plurality of separated angular positions.

54. A method of receiving a wireless transmission in accordance with claim 49 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the cycles of the subcarrier with pulse width modulation.

55. A method of receiving a wireless transmission in accordance with claim 50 wherein:

bits of each of the first and second parallel information streams are modulated on cycles of the subcarrier with each cycle of the subcarrier being modulated with bits at a plurality of separated angular positions.

56. A method of receiving a wireless transmission in accordance with claim 50 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the cycles of the subcarrier with pulse width modulation.

57. A method of receiving a wireless transmission in accordance with claim 51 wherein:

bits of each of the first and second parallel information streams are modulated on cycles of the subcarrier with each cycle of the subcarrier being modulated with bits at a plurality of separated angular positions.

58. A method of receiving a wireless transmission in accordance with claim 51 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the cycles of the subcarrier with pulse width modulation.

59. A method of receiving a wireless transmission in accordance with claim 52 wherein:

bits of each of the first and second parallel information streams are modulated on cycles of the subcarrier with each cycle of the subcarrier being modulated with bits at a plurality of separated angular positions.

60. A method of receiving a wireless transmission in accordance with claim 52 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the cycles of the subcarrier with pulse width modulation.

61. A method of receiving a wireless transmission in accordance with claim 51 wherein:

the integral is calculated by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

62. A method of receiving a wireless transmission in accordance with claim 61 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

63. A method of receiving a wireless transmission in accordance with claim 52 wherein:

the integral is calculated by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

64. A method of receiving a wireless transmission in accordance with claim 63 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

65. A method of receiving a wireless transmission in accordance with claim 57 wherein:

the integral is calculated by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

66. A method of receiving a wireless transmission in accordance with claim 65 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

67. A method of receiving a wireless transmission in accordance with claim 58 wherein:

the integral is calculated by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

68. A method of receiving a wireless transmission in accordance with claim 67 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

69. A method of receiving a wireless transmission in accordance with claim 59 wherein:

the integral is calculated by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

70. A method of receiving a wireless transmission in accordance with claim 69 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

71. A method of receiving a wireless transmission in accordance with claim 60 wherein:

the integral is calculated by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

72. A method of receiving a wireless transmission in accordance with claim 71 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

73. Receiving circuitry for receiving a wireless transmission of information which is subject to fading for a time interval with a radio frequency carrier modulated with a subcarrier with the subcarrier being modulated with first and second encoded identical information streams to produce first and second parallel information streams modulating cycles of the subcarrier with the first parallel information stream containing the first encoded information stream and with the second parallel information stream containing the second encoded information stream with the first and second parallel information streams being transmitted with a time delay interval between the first and second parallel information streams modulating the subcarrier which is equal to or greater than the time interval for transmission to a computer by an information transmission medium comprising:

a detector for detecting the first and second parallel information streams which have been transmitted with the radio frequency carrier;

a processor, coupled to the detector and responsive to the detected parallel streams, for determining if faded information is present in at least one of the detected first and second parallel information streams received and in response to determined faded information replacing the faded information caused by a fade with replacement information from at least one of the first and second parallel information streams which is time offset at transmission from the faded information by the time delay interval and outputting error free transmitted information including the replacement information; and

an interface, for connection to the an information transmission medium and coupled to the processor, for receiving the outputted error free transmitted information and in response to connection to the information transmission medium transmitting the outputted error free transmitted information to the information transmission medium for transmission to the computer; and

wherein

the processor places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and controls replacement of each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

74. Receiving circuitry in accordance with claim 73 wherein:

the first and second encoded information streams each comprises frames of information with each frame having a plurality of bits encoding error correction code and a plurality of bits encoding the information with the error correction code of the first encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the first parallel information stream and the error correction code of the second encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the second parallel information stream; and

the determination of faded information by the processor is performed by determining that the error correction bits cannot correct an error detected by processing the frames of the first and second parallel information streams with the error correction code using the plurality of bits of error correction code.

75. Receiving circuitry in accordance with claim 73 wherein:

the processor comprises a digital signal processor for processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams; and

wherein

the digital signal processor processes the first and second parallel information streams containing the substituted numerical values for determining if the faded information is present.

76. Receiving circuitry in accordance with claim 74 wherein:

the processor comprises a digital signal processor for processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams; and

wherein

the digital signal processor processes the first and second parallel information streams containing the substituted numerical values for determining if the faded information is present.

77. Receiving circuitry in accordance with claim 73 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated by bits at a plurality of separated angular positions.

78. Receiving circuitry in accordance with claim 73 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the subcarrier with pulse width modulation.

79. Receiving circuitry in accordance with claim 74 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated by bits at a plurality of separated angular positions.

80. Receiving circuitry in accordance with claim 74 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the subcarrier with pulse width modulation.

81. Receiving circuitry in accordance with claim 75 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated by bits at a plurality of separated angular positions.

82. Receiving circuitry in accordance with claim 75 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the subcarrier with pulse width modulation.

83. Receiving circuitry in accordance with claim 76 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated by bits at a plurality of separated angular positions.

84. Receiving circuitry in accordance with claim 76 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the subcarrier with pulse width modulation.

85. Receiving circuitry in accordance with claim 75 wherein:

the digital signal processor calculates the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

86. Receiving circuitry in accordance with claim 85 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

87. Receiving circuitry in accordance with claim 76 wherein:

the digital signal processor calculates the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

88. Receiving circuitry in accordance with claim 87 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

89. Receiving circuitry in accordance with claim 81 wherein:

the digital signal processor calculates the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

90. Receiving circuitry in accordance with claim 89 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

91. Receiving circuitry in accordance with claim 82 wherein:

the digital signal processor calculates the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

92. Receiving circuitry in accordance with claim 91 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

93. Receiving circuitry in accordance with claim 83 wherein:

the digital signal processor calculates the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

94. Receiving circuitry in accordance with claim 93 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

95. Receiving circuitry in accordance with claim 84 wherein:

the digital signal processor calculates the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

96. Receiving circuitry in accordance with claim 95 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

97. A method of receiving a wireless transmission of information subject to fading for a time interval with receiving circuitry with a radio frequency carrier modulated with a subcarrier with the subcarrier being modulated with identical first and second encoded information streams to produce first and second parallel information streams modulating cycles of the subcarrier with the first parallel information stream containing the first encoded information stream and with the second parallel information stream containing the second encoded information stream with the first and second parallel information streams being transmitted with a time delay interval between the first and second parallel streams as modulated on the subcarrier which is equal to or greater than the time interval for transmission to a computer through an information transmission medium comprising the steps:

detecting the first and second parallel information streams which have been transmitted with the radio frequency carrier;

determining if faded information is present in at least one of the detected first and second parallel information streams by processing the detected parallel information streams and in response to determined faded information replacing the faded information caused by an fade with replacement information from at least one of the first and second parallel information streams which is time offset from the faded information at transmission by the time delay interval, and outputting error free transmitted information including the replacement information; and

wherein

an error marker is placed within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replacing each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free wirelessly transmitted information;

receiving the outputted error free transmitted information with an interface; and

transmitting the error free wirelessly transmitted information from the interface to the information transmission medium and processing the error free transmitted information with the computer coupled to the information transmission medium.

98. A method of receiving a wireless transmission in accordance with claim 97 wherein:

the first and second encoded information streams each comprise frames of information with each frame having a plurality of bits of error correction code and a plurality of bits encoding the information with the error correction code of the first encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the first parallel information stream and the error correction code of the second encoded information stream not being capable of correcting for a fade of the time interval producing faded information in the second parallel information stream; and

the determination if faded information is present is performed by determining that the plurality of bits of error correction code cannot correct an error detected by processing frames of the first and second parallel information streams with the error correction code using the plurality of error correction bits.

99. A method of receiving a wireless transmission in accordance with claim 97 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams; and

wherein

the first and second parallel information streams containing the substituted numerical values are processed for determining if the faded information is present.

100. A method of receiving a wireless transmission in accordance with claim 98 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams; and

wherein

the first and second parallel information streams containing the substituted numerical values are processed for determining if the faded information is present.

101. A method of receiving a wireless transmission in accordance with claim 97 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated with bits at a plurality of separated angular positions.

102. A method of receiving a wireless transmission in accordance with claim 97 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the cycles of the subcarrier with pulse width modulation.

103. A method of receiving a wireless transmission in accordance with claim 98 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated with bits at a plurality of separated angular positions.

104. A method of receiving a wireless transmission in accordance with claim 98 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the cycles of the subcarrier with pulse width modulation.

105. A method of receiving a wireless transmission in accordance with claim 99 wherein:

bits of each of the first and second parallel information streams are modulate cycles of the subcarrier with each cycle of the subcarrier being modulated with bits at a plurality of separated angular positions.

106. A method of receiving a wireless transmission in accordance with claim 99 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the cycles of the subcarrier with pulse width modulation.

107. A method of receiving a wireless transmission in accordance with claim 100 wherein:

bits of each of the first and second parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated with bits at a plurality of separated angular positions.

108. A method of receiving a wireless transmission in accordance with claim 100 wherein:

groups of bits of the first and second parallel information streams each modulate a width of parts of the cycles of the subcarrier with pulse width modulation.

109. A method of receiving a wireless transmission in accordance with claim 99 wherein:

the integral is calculated by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

110. A method of receiving a wireless transmission in accordance with claim 109 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

111. A method of receiving a wireless transmission in accordance with claim 100 wherein:

the integral is calculated by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

112. A method of receiving a wireless transmission in accordance with claim 111 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

113. A method of receiving a wireless transmission in accordance with claim 105 wherein:

the integral is calculated by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

114. A method of receiving a wireless transmission in accordance with claim 113 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

115. A method of receiving a wireless transmission in accordance with claim 106 wherein:

the integral is calculated by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

116. A method in accordance with claim 115 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

117. A method of receiving a wireless transmission in accordance with claim 107 wherein:

the integral is calculated by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

118. A method of receiving a wireless transmission in accordance with claim 117 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

119. A method of receiving a wireless transmission in accordance with claim 108 wherein:

the integral is calculated by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

120. A method of receiving a wireless transmission in accordance with claim 114 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

121. Circuitry for wireless transmission of information originating from a computer and which is transmitted from the computer on an information transmission medium to transmitting circuitry and transmitted by the transmitting circuitry by modulating a radio frequency carrier modulated with a subcarrier with transmission of the information being subject to fading for a time interval and which receives a wireless transmission of information subject to fading for a time interval with receiving circuitry with a radio frequency carrier modulated with a subcarrier with the subcarrier being modulated with identical first and second encoded information streams to produce first and second parallel information streams modulated on cycles of the subcarrier with the first parallel information stream containing the first encoded information stream and with the second parallel information stream containing the second encoded information stream with the first and second parallel information streams being transmitted with a time delay interval between the first and second parallel streams as modulated on the subcarrier which is equal to or greater than the time interval for transmission to the computer through the information transmission medium wherein:

the receiving circuitry comprises a detector for detecting the transmitted first and second parallel information streams, a processor, coupled to the detector and responsive to the detected parallel information streams, for determining if faded information is present in at least one of the detected first and second parallel information streams and in response to determined faded information replacing the faded information caused by a fade with replacement information from at least one of the first and second parallel information streams which is time offset at transmission from the faded information by the time delay interval and outputting error free transmitted information including the replacement information and an interface for connection to the an information transmission medium and coupled to the processor for receiving the outputted error free transmitted information and in response to connection to the information transmission medium transmitting the outputted error free transmitted information to the information transmission medium for transmission to the computer; and

wherein

the transmitting circuitry comprises a processor which in response to the information to be transmitted provides a first encoded information stream which comprises the information to be transmitted and a second encoded information stream which also comprises the information to be transmitted with the second encoded information stream being delayed by a time delay interval with respect to the first information stream which is equal to or greater than the time interval of the fading and an encoder for modulating the subcarrier with the first and second encoded information streams to produce first and second parallel information streams modulating cycles of the subcarrier with the first parallel information stream containing the first encoded information stream, with the second parallel information stream containing the second encoded information stream and with the first parallel information stream modulating the subcarrier being time displaced from the second parallel information stream by the time delay interval, and a modulator, coupled to the encoder, for modulating the radio frequency carrier with the modulated subcarrier.

122. Circuitry in accordance with claim 121 wherein:

bits of each of the transmitted and received parallel information streams modulate cycles of the subcarrier with each cycle of the subcarrier being modulated by bits at a plurality of separated angular positions.

123. circuitry in accordance with claim 121 wherein:

groups of bits of the first and second parallel information steams of the transmitted and received information streams each modulate a width of parts of the subcarrier with pulse width modulation.

124. Circuitry in accordance with claim 121 wherein:

the received and transmitted parallel information streams comprise frames of information with each frame having a plurality of bits encoding error correction code and a plurality of bits encoding information with the error correction code of the first parallel information stream not being capable of correcting for a fade of the time interval producing faded information in the first parallel information stream and the error correction code of the second parallel information stream not being capable of correcting for a fade of the time interval producing faded information in the second parallel information stream.

125. Circuitry in accordance with claim 122 wherein:

the received and transmitted parallel information streams comprise frames of information with each frame having a plurality of bits encoding error correction code and a plurality of bits encoding information with the error correction code of the first parallel information stream not being capable of correcting for a fade of the time interval producing faded information in the first parallel information stream and the error correction code of the second parallel information stream not being capable of correcting for a fade of the time interval producing faded information in the second parallel information stream.

126. Circuitry in accordance with claim 123 wherein:

the received and transmitted parallel information streams comprise frames of information with each frame having a plurality of bits encoding error correction code and a plurality of bits encoding information with the error correction code of the first parallel information stream not being capable of correcting for a fade of the time interval producing faded information in the first parallel information stream and the error correction code of the second parallel information stream not being capable of correcting for a fade of the time interval producing faded information in the second parallel information stream.

127. Circuitry in accordance with claim 121 wherein:

the time interval of the fading of the received atmospheric transmission is of a length which would cause the receiving circuitry to lose synchronism with the transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

128. Circuitry in accordance with claim 122 wherein:

the time interval of the fading of the received atmospheric transmission is of a length which would cause the receiving circuitry to lose synchronism with the transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

129. Circuitry in accordance with claim 123 wherein:

the time interval of the fading of the received atmospheric transmission is of a length which would cause the receiving circuitry to lose synchronism with the transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

130. Circuitry in accordance with claim 124 wherein:

the time interval of the fading of the received atmospheric transmission is of a length which would cause the receiving circuitry to lose synchronism with the transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

131. Circuitry in accordance with claim 125 wherein:

the time interval of the fading of the received atmospheric transmission is of a length which would cause the receiving circuitry to lose synchronism with the transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

132. Circuitry in accordance with claim 126 wherein:

the time interval of the fading of the received atmospheric transmission is of a length which would cause the receiving circuitry to lose synchronism with the transmitted first and second parallel information streams without replacement of faded information caused by the fade with information offset in time from the faded information by the time delay interval from at least one of the transmitted first and second parallel information streams.

133. Circuitry in accordance with claim 121 wherein:

the processor of the receiving circuitry comprises a digital signal processor which processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams, and processes the first and second parallel information streams containing the substituted numerical values for determining if the faded information is present.

134. Circuitry in accordance with claim 133 wherein:

the digital signal processor calculates the integral which is made by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

135. Circuitry in accordance with claim 134 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

136. Circuitry in accordance with claim 122 wherein:

the processor comprises a digital signal processor which processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams, processes the first and second parallel information streams containing the substituted numerical values for determining if the faded information is present.

137. Circuitry in accordance with claim 136 wherein:

the digital signal processor calculates the integral which is made by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

138. Circuitry in accordance with claim 137 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

139. Circuitry in accordance with claim 123 wherein:

the processor comprises a digital signal processor which processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams, processes the first and second parallel information streams containing the substituted numerical values for determining if the faded information is present.

140. Circuitry in accordance with claim 139 wherein:

the digital signal processor calculates the integral which is made by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

141. Circuitry in accordance with claim 140 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

142. Circuitry in accordance with claim 124 wherein:

the processor comprises a digital signal processor which processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams, processes the first and second parallel information streams containing the substituted numerical values for determining if the faded information is present.

143. Circuitry in accordance with claim 142 wherein:

the digital signal processor calculates the integral which is made by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

144. Circuitry in accordance with claim 143 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

145. Circuitry in accordance with claim 125 wherein:

the processor comprises a digital signal processor which processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams, processes the first and second parallel information streams containing the substituted numerical values for determining if the faded information is present.

146. Circuitry in accordance with claim 145 wherein:

the digital signal processor calculates the integral which is made by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

147. Circuitry in accordance with claim 146 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

148. Circuitry in accordance with claim 126 wherein:

the processor comprises a digital signal processor which processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least a part of an information unit in one of the first and second parallel information streams, processes the first and second parallel information streams containing the substituted numerical values for determining if the faded information is present.

149. Circuitry in accordance with claim 148 wherein:

the digital signal processor calculates the integral which is made by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

150. circuitry in accordance with claim 149 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

151. Circuitry in accordance with claim 121 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

152. Circuitry in accordance with claim 122 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

153. Circuitry in accordance with claim 123 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

154. Circuitry in accordance with claim 124 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

155. Circuitry in accordance with claim 125 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

156. Circuitry in accordance with claim 126 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

157. Circuitry in accordance with claim 127 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

158. Circuitry in accordance with claim 128 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

159. Circuitry in accordance with claim 129 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

160. Circuitry in accordance with claim 130 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

161. Circuitry in accordance with claim 131 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

162. Circuitry in accordance with claim 132 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

163. Circuitry in accordance with claim 133 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

164. Circuitry in accordance with claim 134 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

165. Circuitry in accordance with claim 135 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

166. Circuitry in accordance with claim 136 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

167. Circuitry in accordance with claim 137 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

168. Circuitry in accordance with claim 138 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

169. Circuitry in accordance with claim 139 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

170. Circuitry in accordance with claim 140 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

171. Circuitry in accordance with claim 141 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

172. Circuitry in accordance with claim 142 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

173. Circuitry in accordance with claim 143 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

174. Circuitry in accordance with claim 144 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

175. Circuitry in accordance with claim 145 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

176. Circuitry in accordance with claim 146 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

177. Circuitry in accordance with claim 147 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

178. Circuitry in accordance with claim 148 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

179. Circuitry in accordance with claim 149 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

180. Circuitry in accordance with claim 150 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.

181. Circuitry in accordance with claim 151 wherein:

the processor of the receiving circuitry places an error marker within the detected first and second parallel information streams to mark each faded information unit within the faded information requiring replacement and replaces each error marker within at least one of the first and second parallel information streams with replacement bits within one of the first and second parallel information streams which were time offset at transmission by the time delay interval to produce the error free transmitted information.