Neural semiconductor chip and neural networks incorporated therein
First Claim
1. A base neural network (11(A)) for identifying an input vector (A), said base neural network (11(A)) comprising:
- a neural network (11-(#)) comprised of a plurality of neuron circuits (11-i) being connected in parallel to a data bus and a control bus, each said neuron circuit being in one of two states, said two states being a free state and an engaged state, each said neuron circuit comprising;
means for generating local result signals, said local result signals being individual responses of said neuron circuit to the input vector,means for placing said generated local result signals on a first dedicated bus (NR-BUS) after said neuron is engaged;
means for generating a local output signal (NOUT), said local output signal indicating a vector category or a distance between said input vector and a prototype vector stored in said neuron circuit, andmeans for placing said local output signal (NOUT) on a second dedicated bus (NOUT-BUS) after said neuron is engaged;
logic means (12) for combining said local result signals and generating therefrom corresponding global result signals, and for combining said local output signals and generating therefrom a global output signal (OUT*), said global result signals and said global output signals being on their respective buses (R*-BUS, OUT*-BUS) and merging in a common communication bus (COM*-BUS); and
,means for feeding back at least said global output signal as a feed-back signal (OR) to each of said neuron circuits on a feed-back bus (OR-BUS), thereby allowing the comparison between said local output and said global output signal to generate a local result signal.
4 Assignments
0 Petitions
Accused Products
Abstract
A base neural semiconductor chip (10) including a neural network or unit (11(#)). The neural network (11(#)) has a plurality of neuron circuits fed by different buses transporting data such as the input vector data, set-up parameters, and control signals. Each neuron circuit (11) includes logic for generating local result signals of the "fire" type (F) and a local output signal (NOUT) of the distance or category type on respective buses (NR-BUS, NOUT-BUS). An OR circuit (12) performs an OR function for all corresponding local result and output signals to generate respective first global result (R*) and output (OUT*) signals on respective buses (R*-BUS, OUT*-BUS) that are merged in an on-chip common communication bus (COM*-BUS) shared by all neuron circuits of the chip. In a multi-chip network, an additional OR function is performed between all corresponding first global result and output signals (which are intermediate signals) to generate second global result (R**) and output (OUT**) signals, preferably by dotting onto an off-chip common communication bus (COM**-BUS) in the chip'"'"'s driver block (19). This latter bus is shared by all the base neural network chips that are connected to it in order to incorporate a neural network of the desired size. In the chip, a multiplexer (21) may select either the intermediate output or the global output signal to be fed back to all neuron circuits of the neural network, depending on whether the chip is used in a single or multi-chip environment via a feed-back bus (OR-BUS). The feedback signal is the result of a collective processing of all the local output signals.
214 Citations
40 Claims
-
1. A base neural network (11(A)) for identifying an input vector (A), said base neural network (11(A)) comprising:
-
a neural network (11-(#)) comprised of a plurality of neuron circuits (11-i) being connected in parallel to a data bus and a control bus, each said neuron circuit being in one of two states, said two states being a free state and an engaged state, each said neuron circuit comprising; means for generating local result signals, said local result signals being individual responses of said neuron circuit to the input vector, means for placing said generated local result signals on a first dedicated bus (NR-BUS) after said neuron is engaged; means for generating a local output signal (NOUT), said local output signal indicating a vector category or a distance between said input vector and a prototype vector stored in said neuron circuit, and means for placing said local output signal (NOUT) on a second dedicated bus (NOUT-BUS) after said neuron is engaged; logic means (12) for combining said local result signals and generating therefrom corresponding global result signals, and for combining said local output signals and generating therefrom a global output signal (OUT*), said global result signals and said global output signals being on their respective buses (R*-BUS, OUT*-BUS) and merging in a common communication bus (COM*-BUS); and
,means for feeding back at least said global output signal as a feed-back signal (OR) to each of said neuron circuits on a feed-back bus (OR-BUS), thereby allowing the comparison between said local output and said global output signal to generate a local result signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. A base neural network (11(A)) for identifying an input vector (A), said base neural network comprising:
-
a neural network (11-(#)) comprised of a plurality of neuron circuits (11-i) connected in parallel to a data bus and a control bus, each said neuron circuit being in one of two states, said two states being a free state and an engaged state, each said neuron circuit comprising; means for generating local result signals, said local results being individual responses of said neuron circuit to the input vector, means for placing said generated local results on a first dedicated bus (NR-BUS) after said neuron circuit is engaged, means for generating a local output signal (NOUT), and means for placing said local output signal (NOUT) on a second dedicated bus (NOUT-BUS) after said neuron circuit is engaged; first logic means (12) for combining a group of said local result signals to generate corresponding intermediate result signals and for combining a group of said local output signals to an generate intermediate output signal (OUT*), said intermediate signals being available on their respective buses (R*-BUS, OUT*-BUS) and merging in a first common communication bus (COM*-BUS); second logic means for combining at least two of each of said intermediate result signals to generate corresponding second global result signals and for combining at least two of said intermediate output signals to generate a global output signal (OUT**), said global result signal and said global output signal being available on their respective buses (R**-BUS, OUT**-BUS) and merging in a second common communication bus (COM**-BUS); and
,means for feeding back at least said global output signal to each of said neuron circuits as a feed-back signal (OR) on a feed-back bus (OR-BUS), thereby allowing the comparison between corresponding said local output signal and said global output signal to generate a local result signal. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 40)
-
-
31. A base neural semiconductor chip (10) comprising:
-
a neural network (11(#)) comprised of a plurality of neuron circuits (11-i) connected in parallel to a data and a control bus, each said neuron circuit being in one of two states, said two states being a free state and an engaged state, each said neuron circuit comprising; means for generating local result signals said local result signals being individual responses of said neuron circuit to an input vector, means for placing said generated local result signals on a first dedicated bus (NR-BUS), after said neuron is engaged, and means for generating a local output signal (NOUT), said local output signal indicating a vector category or a distance between said input vector and a prototype vector stored in said neuron circuit, and means for placing said local output on a second dedicated bus (NOUT-BUS) after said neuron is engaged; logic means for combining said local result signals and generating therefrom corresponding global result signals and, for combining said local output signals and generating therefrom global output signals (OUT*) said global result signals and said global output signals being on their respective buses (R*-BUS, OUT*-BUS) and merging in a common communication bus (COM*-BUS); and means for feeding back at least said global output signal as a feedback signal (OR) to each of said neuron circuits on a feedback bus (OR-BUS), thereby allowing the comparison between corresponding said local output signals and said global output signal to generate said local result signals. - View Dependent Claims (32)
-
-
33. A base neural semiconductor chip (10) for use as a unit in a multi-chip network, said base neural semiconductor chip comprising:
-
a neuron unit (11(#)) comprised of a plurality of neuron circuits (11-i) connected in parallel to a data bus and a control bus, each said neuron circuit being in one of two states, said two states being a free state and an engaged state, each said neuron circuit comprising; means for generating local result signals said local result signals being individual responses of said neuron circuit to an input vector, means for placing said generated local result signals on a first dedicated bus (NR-BUS) after said neuron is engaged, and means for generating a local output signal (NOUT), said local output signal indicating a vector category or a distance between said input vector and a prototype vector stored in said neuron circuit, and means for placing said local output signal on a second dedicated bus (NOUT-BUS); first logic means for combining a group of said local result signals and generating therefrom corresponding first intermediate result signals and for combining a group of first local output signals generating therefrom a first intermediate output signal (OUT*), said intermediate result signals and said intermediate output signals being available on their respective buses (R*-BUS, OUT*-BUS) and merging in a first common communication bus (COM*-BUS); second logic means for combining at least two of each of said intermediate result signals to generate corresponding second global result signals and for combining at least two of said intermediate output signals to generate a global output signal (OUT**) on their respective buses (R**-BUS, OUT**-BUS) of a second common communication bus (COM**-BUS), said second common communication bus being commonly connectable to other base neural semiconductor chips in a network of said chips; and
,means for feeding back at least said global output signal as a feedback signal (OR) to each of said neuron circuits on a feedback bus (OR-BUS) thereby allowing the comparison between corresponding said local output signal and said global output signal to generate said local result signals. - View Dependent Claims (34, 35, 36, 37, 38, 39)
-
Specification